MCF5328CVM240 Freescale Semiconductor, MCF5328CVM240 Datasheet - Page 40

• Manufacturer Part Number: MCF5328CVM240
• Description: IC MCU 32BIT 240MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF532xr

Specifications of MCF5328CVM240

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSI, UART/USART, USB, USB OTG
• Peripherals: DMA, LCD, PWM, WDT
• Number Of I /o: 94
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Program Memory Size: 16KB
• Cpu Speed: 240MHz
• Embedded Interface Type: CAN, I2C, MAC, Ethernet, QSPI, UART
• Rohs Compliant: Yes
• Family Name: MPC5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 240MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (max): 1.6/1.95/2.75/3.6V
• Operating Supply Voltage (min): 1.4/1.7/2.25/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Electrical Characteristics
5.18
40
1
Num
J10
J11
J12
J13
J14
JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.
J1
J2
J3
J4
J5
J6
J7
J8
J9
QSPI_CS[3:0]
QSPI_DOUT
QSPI_CLK
QSPI_DIN
JTAG and Boundary Scan Timing
TCLK Frequency of Operation
TCLK Cycle Period
TCLK Clock Pulse Width
TCLK Rise and Fall Times
Boundary Scan Input Data Setup Time to TCLK Rise
Boundary Scan Input Data Hold Time after TCLK Rise
TCLK Low to Boundary Scan Output Data Valid
TCLK Low to Boundary Scan Output High Z
TMS, TDI Input Data Setup Time to TCLK Rise
TMS, TDI Input Data Hold Time after TCLK Rise
TCLK Low to TDO Data Valid
TCLK Low to TDO High Z
TRST Assert Time
TRST Setup Time (Negation) to TCLK High
QS3
MCF532x ColdFire
Characteristics
QS1
Table 29. JTAG and Boundary Scan Timing
QS2
Figure 27. QSPI Timing
1
®
Microprocessor Data Sheet, Rev. 5
Symbol
t
t
t
t
t
t
t
t
TAPBHT
TRSTST
TAPBST
TRSTAT
TDODV
TDODZ
f
t
t
BSDST
BSDHT
t
t
t
JCYC
JCYC
JCRF
BSDV
BSDZ
JCW
QS4
Min
100
DC
26
26
10
10
4
0
4
0
0
4
0
0
QS5
Max
Freescale Semiconductor
1/4
33
33
26
—
—
—
—
—
—
—
—
3
8
f
Unit
t
sys/3
CYC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns