ST16C550CQ48-F Exar Corporation, ST16C550CQ48-F Datasheet - Page 16

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ST16C550CQ48-F

Manufacturer Part Number
ST16C550CQ48-F
Description
IC UART FIFO 16B SGL 48TQFP
Manufacturer
Exar Corporation
Type
UART with 16-byte FIFOsr
Datasheet

Specifications of ST16C550CQ48-F

Number Of Channels
1, UART
Package / Case
48-TQFP
Features
*
Fifo's
16 Byte
Voltage - Supply
2.97 V ~ 5.5 V
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
1.5 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.97 V
Supply Current
3 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V, 5 V
No. Of Channels
1
Supply Voltage Range
2.97V To 5.5V
Operating Temperature Range
0°C To +70°C
Digital Ic Case Style
TQFP
No. Of Pins
48
Filter Terminals
SMD
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
1016-1260

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Part Number
Manufacturer
Quantity
Price
Part Number:
ST16C550CQ48-F
Manufacturer:
Exar Corporation
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Manufacturer:
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ST16C550
Interrupt Status Register (ISR)
The ST16C550 provides four levels of prioritized inter-
rupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six
interrupt status bits. Performing a read cycle on the ISR
will provide the user with the highest pending interrupt
level to be serviced. No other interrupts are acknowl-
edged until the pending interrupt is serviced. Whenever
the interrupt status register is read, the interrupt status
is cleared. However it should be noted that only the
current pending interrupt is cleared by the read. A lower
level interrupt may be seen after rereading the interrupt
status bits. The Interrupt Source Table 5 (below) shows
the data values (bit 0-3) for the four prioritized interrupt
levels and the interrupt sources associated with each
of these interrupt levels:
Priority
Level
Rev. 5.01
X
1
2
2
3
4
Table 5, INTERRUPT SOURCE TABLE
Bit-3 Bit-2 Bit-1 Bit-0
0
0
0
1
0
0
[ISR]
0
1
1
1
0
0
0
1
0
0
1
0
1
0
0
0
0
0
No interrupt pending
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data time out)
TXRDY ( Transmitter Holding Register Empty)
MSR (Modem Status Register)
Source of the interrupt
16

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