ST16C550CQ48-F Exar Corporation, ST16C550CQ48-F Datasheet - Page 9

• Manufacturer Part Number: ST16C550CQ48-F
• Description: IC UART FIFO 16B SGL 48TQFP
• Manufacturer: Exar Corporation
• Type: UART with 16-byte FIFOsr

Specifications of ST16C550CQ48-F

• Number Of Channels: 1, UART
• Package / Case: 48-TQFP
• Features: *
• Fifo's: 16 Byte
• Voltage - Supply: 2.97 V ~ 5.5 V
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 1.5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 3 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V, 5 V
• No. Of Channels: 1
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 48
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1260

FIFO Operation
The 16 byte transmit and receive data FIFO’s are
enabled by the FIFO Control Register (FCR) bit-0.
With 16C550 devices, the user can set the receive
trigger level but not the transmit trigger level. The
receiver FIFO section includes a time-out function to
ensure data is delivered to the external CPU. An
interrupt is generated whenever the Receive Holding
Register (RHR) has not been read following the load-
ing of a character or the receive trigger level has not
been reached.
Time-out Interrupts
When two interrupt conditions have the same priority,
it is important to service these interrupts correctly.
Receive Data Ready and Receive Time Out have the
same interrupt priority (when enabled by IER bit-0).
The receiver issues an interrupt after the number of
characters have reached the programmed trigger level.
In this case the ST16C550 FIFO may hold more
Rev. 5.01
Baud Rate Generator Registers (DLL/DLM). Accessible only when LCR bit-7 is set to 1.
A2
0
0
0
0
1
1
1
1
0
0
Table 2, INTERNAL REGISTER DECODE
General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR):
A1
0
0
1
1
0
0
1
1
0
0
A0
0
1
0
1
0
1
0
1
0
1
READ MODE
Receive Holding Register
Interrupt Enable Register
Interrupt Status Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
9
characters than the programmed trigger level. Fol-
lowing the removal of a data byte, the user should
recheck LSR bit-0 for additional characters. A Re-
ceive Time Out will not occur if the receive FIFO is
empty. The time out counter is reset at the center of
each stop bit received or each time the receive
holding register (RHR) is read (see Figure 10, Re-
ceive Time-out Interrupt). The actual time out value is
T (Time out length in bits) = 4 X P (Programmed word
length) + 12. To convert the time out value to a
character value, the user has to consider the com-
plete word length, including data information length,
start bit, parity bit, and the size of stop bit, i.e., 1X,
1.5X, or 2X bit times.
Example -A: If the user programs a word length of 7,
with no parity and one stop bit, the time out will be:
T = 4 X 7( programmed word length) +12 = 40 bit times.
The character time will be equal to 40 / 9 = 4.4
characters, or as shown in the fully worked out ex-
WRITE MODE
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
Reserved
Reserved
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
ST16C550