XR16L788CQ-F Exar Corporation, XR16L788CQ-F Datasheet - Page 28

• Manufacturer Part Number: XR16L788CQ-F
• Description: IC UART 64B 3.3V OCTAL 100QFP
• Manufacturer: Exar Corporation
• Type: IrDA or RS- 485r

Specifications of XR16L788CQ-F

• Number Of Channels: 8
• Package / Case: 100-BQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 5 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V or 5 V
• No. Of Channels: 8
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: QFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1283

XR16L788
HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART
T
A
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
0 0 1 0
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 0
ABLE
A3-A0
DDRESS
12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION.
TXCNT
TXTRG
FCTR
N
MCR
MSR
MSR
RHR
DLM
THR
FCR
LCR
SPR
EFR
R
DLL
LSR
IER
ISR
AME
EG
R
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EAD
RITE
W
W
W
W
R
R
R
R
/
RX FIFO
RX FIFO
DSR# Int.
Enable
Trigger
Enable
RS485
Enable
Divisor
E
Enable
FIFOs
DLY-3
Pres-
Table
B
CTS/
BRG
caler
TRG
DSR
Bit-7
Bit-7
Bit-7
Bit-7
CTS/
Bit-7
Auto
Bit-7
Bit-7
RROR
Bit-1
CD
IT
0
0
-7
RX FIFO
DTR# Int.
Trigger
Enable
Set TX
Enable
RS485
Enable
Enable
FIFOs
Empty
Break
DLY-2
B
Table
RTS/
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
TRG
Auto
DTR
Bit-6
Bit-6
RTS/
TSR
Bit-0
IR
RI
IT
0
0
-6
TX FIFO
Xon/Xoff/
Sp. Char.
Set Par-
XonAny
Special
Trigger
Enable
RS485
RS485
Empty
Select
Enable
Delta-
DLY-1
B
Flow
DSR
Char
Bit-5
Bit-5
Bit-5
Bit-5
THR
Bit-5
Auto
Bit-5
Bit-5
Cntl
Int.
ity
IT
0
0
0
-5
28
Xoff/spe-
TX FIFO
RX Input
cial char
Lopback
Invert IR
Internal
FCR[5:4],
MCR[7:5]
Trigger
IER [7:4],
ISR [5:4],
MSR[7:4]
Enable
RS485
Break
DLY-0
Parity
B
Enable
Even
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
CTS
RX
IT
0
0
-4
Hyst Bit-
Framing
Modem
Enable
Source
Enable
Status
Parity
Mode
OP2
B
Delta
RTS/
DMA
Error
Soft-
ware
Flow
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
CD#
Bit-3
DTR
Bit-3
Bit-3
Bit-3
Cntl
INT
Int.
RX
IT
0
3
-3
2
TX FIFO
Stop Bits
Flow Sel
Hyst Bit-
RX Line
RX Par-
ity Error
Source
Enable
Status
Reset
OP1
B
Delta
RTS/
RTS/
ware
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
DTR
Bit-2
DTR
Soft-
Flow
Bit-2
Bit-2
Bit-2
Cntl
INT
RI#
Int.
IT
0
2
-2
2
S
HADED BITS ARE ENABLED BY
RX FIFO
Pin Con-
Hyst Bit-
Overrun
Enable
Source
Length
Empty
DSR#
Reset
RTS#
Word
B
Delta
RTS/
Soft-
ware
Flow
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
DTR
Bit-1
Bit-1
Bit-1
Cntl
INT
TX
Int.
trol
RX
IT
0
1
-1
Pin Con-
RX Data
RX Data
Hyst Bit-
Source
Enable
Enable
Length
Ready
FIFOs
DTR#
CTS#
B
Word
Delta
RTS/
ware
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
DTR
Soft-
Flow
Bit-0
Bit-0
Bit-0
Cntl
INT
Int.
trol
IT
0
0
-0
REV. 1.2.3
User Data
C
LCR[7]=0
LCR[7]=0
LCR[7]=1
LCR[7]=1
EFR B
OMMENT
IT
-4.