ST16C654DIQ64-F Exar Corporation, ST16C654DIQ64-F Datasheet - Page 14

• Manufacturer Part Number: ST16C654DIQ64-F
• Description: IC UART FIFO 64B QUAD 64LQFP
• Manufacturer: Exar Corporation

Specifications of ST16C654DIQ64-F

• Number Of Channels: 4, QUART
• Package / Case: 64-LQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS232
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 1.5 Mbps
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• No. Of Channels: 4
• Uart Features: Infrared (IrDA) Encoder/Decoder
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1271

ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set
when TSR/FIFO becomes empty.
F
F
2.9.2
2.9.3
IGURE
IGURE
7. T
8. T
Transmitter Operation in non-FIFO Mode
Transmitter Operation in FIFO Mode
RANSMITTER
RANSMITTER
Auto CTS Flow Control (CTS# pin)
(Xoff1/2 and Xon1/2 Reg.
Auto Software Flow Control
Flow Control Characters
Clock
16X Clock
16X
O
O
Data
Byte
PERATION IN NON
PERATION IN
Data Byte
Transm it Shift Register (TSR)
FIFO
Transm it
-FIFO M
Register
Holding
(THR)
AND
Transm it Data Shift Register
F
LOW
ODE
RX FIFO
(TSR)
14
THR
C
ONTROL
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
M
THR Interrupt (ISR bit-1) falls
below the programm ed Trigger
Level and then when becom es
em pty. FIFO is Enabled by FCR
bit-0=1
ODE
M
S
B
TXNO FIFO 1
L
S
B
T XF IF O 1
xr
REV. 5.0.2