XR16C864IQ-F Exar Corporation, XR16C864IQ-F Datasheet - Page 14
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XR16C864IQ-F
Manufacturer Part Number
XR16C864IQ-F
Description
IC UART FIFO 128B QUAD 100QFP
Manufacturer
Exar Corporation
Type
Quad UART with 128-byte FIFOsr
Datasheet
1.XR16C864IQ-F.pdf
(51 pages)
Specifications of XR16C864IQ-F
Number Of Channels
4, QUART
Package / Case
100-BQFP
Features
*
Fifo's
128 Byte
Protocol
RS232, RS485
Voltage - Supply
2.97 V ~ 5.5 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
2 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.97 V
Supply Current
3 mA to 6 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2.97 V to 5.5 V
No. Of Channels
4
Uart Features
Tx/Rx FIFO Counters
Supply Voltage Range
2.97V To 5.5V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
QFP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
1016-1277
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR16C864IQ-F
Manufacturer:
NAIS
Quantity:
420
Company:
Part Number:
XR16C864IQ-F
Manufacturer:
Exar Corporation
Quantity:
10 000
XR16C864
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the TX FIFO and TSR are
reported in the Line Status Register (LSR bit-5 and bit-6).
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 128 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
The host may fill the transmit FIFO with up to 128 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the TX FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when
the FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set
when TSR/TX FIFO becomes empty.
F
F
2.12.1
2.12.2
2.12.3
IGURE
IGURE
6. T
7. T
Transmit Holding Register (THR) - Write Only
Transmitter Operation in non-FIFO Mode
Transmitter Operation in FIFO Mode
RANSMITTER
RANSMITTER
Auto CTS Flow Control (CTS# pin)
(Xoff1/2 and Xon1/2 Reg.
Auto Software Flow Control
Flow Control Characters
Clock
16X Clock
16X
O
O
Data
Byte
PERATION IN NON
PERATION IN
Data Byte
Transm it Shift Register (TSR)
FIFO
Transm it
-FIFO M
Register
Holding
(THR)
AND
Transm it Data Shift Register
F
LOW
ODE
RX FIFO
(TSR)
14
THR
C
ONTROL
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
M
THR Interrupt (ISR bit-1) falls
below the programmed Trigger
Level and then when becomes
empty. FIFO is Enabled by FCR
bit-0=1
ODE
M
S
B
TXNOFIFO 1
L
S
B
T XF IF O 1
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REV. 2.0.1