XR16C864IQ-F Exar Corporation, XR16C864IQ-F Datasheet - Page 37
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XR16C864IQ-F
Manufacturer Part Number
XR16C864IQ-F
Description
IC UART FIFO 128B QUAD 100QFP
Manufacturer
Exar Corporation
Type
Quad UART with 128-byte FIFOsr
Datasheet
1.XR16C864IQ-F.pdf
(51 pages)
Specifications of XR16C864IQ-F
Number Of Channels
4, QUART
Package / Case
100-BQFP
Features
*
Fifo's
128 Byte
Protocol
RS232, RS485
Voltage - Supply
2.97 V ~ 5.5 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
2 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.97 V
Supply Current
3 mA to 6 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2.97 V to 5.5 V
No. Of Channels
4
Uart Features
Tx/Rx FIFO Counters
Supply Voltage Range
2.97V To 5.5V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
QFP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
1016-1277
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR16C864IQ-F
Manufacturer:
NAIS
Quantity:
420
Company:
Part Number:
XR16C864IQ-F
Manufacturer:
Exar Corporation
Quantity:
10 000
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REV. 2.0.1
EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 to be
modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values. This
feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it is
recommended to leave it enabled, logic 1.
EFR[5]: Special Character Detect Enable
Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR
bits 5-7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7are set to a logic 0 to be compatible with ST16C550 mode (default).
Logic 1 = Enables the above-mentioned register bits to be modified by the user.
Logic 0 = Special Character Detect Disabled (default).
Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt, if enabled via IER bit-5.
EFR
C
ONT
X
X
X
0
0
1
0
1
1
0
1
0
BIT
-3
-3
EFR
C
ONT
X
X
X
0
0
0
1
1
0
1
1
0
BIT
-2
-2
T
ABLE
EFR
C
ONT
17: S
X
X
X
X
0
0
1
0
1
1
1
1
BIT
-1
-1
OFTWARE
EFR
C
ONT
X
X
X
X
0
0
0
1
1
1
1
1
F
BIT
37
LOW
-0
-0
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
C
No TX and RX flow control (default and reset)
No transmit flow control
Transmit Xon1, Xoff1
Transmit Xon2, Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2
No receive flow control
Receiver compares Xon1, Xoff1
Receiver compares Xon2, Xoff2
Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
No transmit flow control,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
ONTROL
T
RANSMIT AND
F
UNCTIONS
R
ECEIVE
S
OFTWARE
F
LOW
XR16C864
C
ONTROL