XR16C864IQ-F Exar Corporation, XR16C864IQ-F Datasheet - Page 3
![IC UART FIFO 128B QUAD 100QFP](/photos/29/6/290689/tqfp100_sml.jpg)
XR16C864IQ-F
Manufacturer Part Number
XR16C864IQ-F
Description
IC UART FIFO 128B QUAD 100QFP
Manufacturer
Exar Corporation
Type
Quad UART with 128-byte FIFOsr
Datasheet
1.XR16C864IQ-F.pdf
(51 pages)
Specifications of XR16C864IQ-F
Number Of Channels
4, QUART
Package / Case
100-BQFP
Features
*
Fifo's
128 Byte
Protocol
RS232, RS485
Voltage - Supply
2.97 V ~ 5.5 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
2 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.97 V
Supply Current
3 mA to 6 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2.97 V to 5.5 V
No. Of Channels
4
Uart Features
Tx/Rx FIFO Counters
Supply Voltage Range
2.97V To 5.5V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
QFP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
1016-1277
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR16C864IQ-F
Manufacturer:
NAIS
Quantity:
420
Company:
Part Number:
XR16C864IQ-F
Manufacturer:
Exar Corporation
Quantity:
10 000
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REV. 2.0.1
ORDERING INFORMATION
PIN DESCRIPTIONS
Pin Description
DATA BUS INTERFACE
(R/W#)
(N.C.)
CSA#
(CS#)
CSB#
CSC#
N
IOW#
IOR#
(A3)
(A4)
D7
D6
D5
D4
D3
D2
D1
D0
A2
A1
A0
AME
XR16C864CQ
P
XR16C864IQ
ART
N
100-QFP
UMBER
P
37
38
39
95
94
93
92
91
90
89
88
66
15
13
17
64
IN
#
T
I/O
YPE
I
I
I
I
I
I
Address data lines [2:0]. These 3 address lines select one of the internal registers in
UART channels A-D during a data bus transaction.
Data bus lines [7:0] (bidirectional).
When 16/68# pin is at logic 1, the Intel bus interface is selected and this input becomes
read strobe (active low). The falling edge instigates an internal read cycle and retrieves
the data byte from an internal register pointed by the address lines [A2:A0], puts the data
byte on the data bus to allow the host processor to read it on the rising edge.
When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input is not
used.
When 16/68# pin is at logic 1, it selects Intel bus interface and this input becomes write
strobe (active low). The falling edge instigates the internal write cycle and the rising edge
transfers the data byte on the data bus to an internal register pointed by the address lines.
When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input
becomes read (logic 1) and write (logic 0) signal.
When 16/68# pin is at logic 1, this input is chip select A (active low) to enable channel A in
the device.
When 16/68# pin is at logic 0, this input becomes the chip select (active low) for the
Motorola bus interface.
When 16/68# pin is at logic 1, this input is chip select B (active low) to enable channel B in
the device.
When 16/68# pin is at logic 0, this input becomes address line A3 which is used for chan-
nel selection in the Motorola bus interface.
When 16/68# pin is at logic 1, this input is chip select C (active low) to enable channel C
in the device.
When 16/68# pin is at logic 0, this input becomes address line A4 which is used for chan-
nel selection in the Motorola bus interface.
100-Lead QFP
100-Lead QFP
P
ACKAGE
O
3
PERATING
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
-40°C to +85°C
0°C to +70°C
D
T
ESCRIPTION
EMPERATURE
R
ANGE
D
EVICE
Active
Active
XR16C864
S
TATUS