73S8014RN-DB Maxim Integrated Products, 73S8014RN-DB Datasheet
73S8014RN-DB
Specifications of 73S8014RN-DB
Related parts for 73S8014RN-DB
73S8014RN-DB Summary of contents
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TM Simplifying System Integration 73S8014R/RN/RT 20SO Demo Board User Manual July, 2008 Rev. 1.0 UM_8014_010 ...
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Demo Board User Manual © 2008 Teridian Semiconductor Corporation. All rights reserved. Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration is a trademark of Teridian Semiconductor Corporation. All other trademarks are the ...
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UM_8014_010 1 Introduction ......................................................................................................................................... 4 1.1 General ......................................................................................................................................... 4 1.2 Safety and ESD Notes .................................................................................................................. 4 1.3 Getting Started .............................................................................................................................. 5 1.4 Recommended Operating Conditions and Absolute Maximum Ratings ...................................... 6 1.4.1 Recommended Operating Conditions ...
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... VCC. See the applicable data sheet for further detail. The 73S8014R uses the clock divider signals CLKDIV1 and CLKDIV2 to select between a divide and 8 for the smart card CLK output. The 73S8014RN and 73S8014RT have been redefined to select between divide and 6 to support NDS applications. ...
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... Apply clock source to pin Apply 3.3V (1) or GND (0) to CLKDIV1 and CLKDIV2 pins allows the following: o CLKDIV1 = CLKDIV2 = 0 - 73S8014R clock frequency = SCLK/8 - 73S8014RN/RT clock frequency = SCLK/6 - CLKDIV1 = 0, CLKDIV2 =1 clock frequency = SCLK/4 (all) - CLKDIV1 = 1, CLKDIV2 =0 clock frequency = SCLK (all) - CLKDIV1 = CLKDIV2 = 1 - • ...
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Demo Board User Manual 1.4 Recommended Operating Conditions and Absolute Maximum Ratings 1.4.1 Recommended Operating Conditions Parameter Supply Voltage V DD Supply Voltage V PC Ambient Operating Temperature Input Voltage for Digital Inputs 1.4.1 Absolute Maximum Ratings: Operation ...
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UM_8014_010 External clock source. JP1 must be in position SCLK when use of an external clock. Otherwise, pin SCLK can be left open. SCLK IOUC OFF GND 2 VPC V Power PC Supply: +4.5V to +5.5V (5V Typ.) /200mA Rev. ...
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Design Considerations 2.1 General Layout Rules Keep the CLK signal as short as possible and with few bends in the trace. Keep route of the CLK trace to one layer (avoid vias to other plane). Keep CLK trace away ...
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Demo Board User Manual 3 Use of the Board: Hardware 3.1 Board Description: Jumpers, Switches and Test Points The items described in the following tables refer to the flags in Figure 2.1 Schemati Item # c & PCB ...
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Figure 3: TERIDIAN 73S8014R/RN/RT Demo Board: Board Description Rev. 1 ...
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Demo Board User Manual 3.2 73S8014R/RN/RT Pin Description Table 2: 73S8014R/RN/RT Pin Description: Card Interface Name Pin # Description I/O 14 Card I/O: Data signal to/from card. Includes a pull-up resistor to V RST 15 Card reset: provides ...
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UM_8014_010 Table 5: 73S8014R/RN/RT Pin Description: Microcontroller Interface Name Pin # CMDVCC (R) CMDVCC% 6 (RN/RT) 5V/#V (R) CMDVCC# 7 (RN/RT) CLKDIV1 20 CLKDIV2 5 OFF 1 RSTIN 2 I/OUC 3 Rev. 1.0 73S8014R/RN/RT 20SO Demo Board User Manual Description ...
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... Demo Board User Manual 3.3 73S8014R/RN Pinout (SO20 – Top View) OFF 1 RSTIN 2 I/OUC 3 VPC 4 CLKDIV2 5 CMDVCC 6 5V/#V 7 GND 8 XTALIN 9 XTALOUT 73S8014R/ 16 73S8014RN UM_8014_010 CLKDIV1 PRES VCC CLK GND RST I/O VDD VDDF_ADJ GND Rev. 1.0 ...
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UM_8014_010 3.4 73S8014RT PINOUT (20SO – Top View) OFF 1 RSTIN 2 I/OUC 3 VPC 4 CLKDIV2 5 CMDVCC% 6 CMDVCC# 7 GND 8 XTALIN 9 XTALOUT 10 Rev. 1.0 73S8014R/RN/RT 20SO Demo Board User Manual ...
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Demo Board User Manual 4 Appendix This appendix includes the following tables and drawings of the PCB of the Evaluation Board: • Electrical Schematic • Bill of Materials • Silk Screen Layer – Top side • Silk Screen ...
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UM_8014_010 Figure 4: TERIDIAN 73S8014R/RN/RT 20SO Demo Board: Electrical Schematic J1 SCLK 1 2 SIO 3 4 OFFB 5 GND 6 GND 7 GND 8 +5V 9 +5V 10 SSM_110_L_SV J2 SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK 1 ...
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Demo Board User Manual Table 6: TERIDIAN 73S8014R/RN/RT 20SO Demo Board: Bill of Material Item Qty Reference Part 1 3 C1, C3, C10 CAP 10UF 6.3V CERAMIC X5R 0805 2 1 C11 CAP 1.0UF 6.3V CERAMIC X5R 0603 ...
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UM_8014_010 Figure 5: TERIDIAN 73S8014R/RN/RT 20SO Demo Board: Top View Figure 6: TERIDIAN 73S8014R/RN/RT 20SO Demo Board: Bottom View Rev. 1.0 73S8014R/RN/RT 20SO Demo Board User Manual 19 ...
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Demo Board User Manual Figure 7: TERIDIAN 73S8014R/RN/RT 20SO Demo Board: Top Signal Layer Figure 8: TERIDIAN 73S8014R/RN/RT 20SO Demo Board: Middle Layer 1, Ground Plane. 20 UM_8014_010 Rev. 1.0 ...
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UM_8014_010 Figure 9: TERIDIAN 73S8014R/RN/RT 20SO Demo Board: Middle Layer 2, Supply Plane. Figure 10: TERIDIAN 73S8014R/RN/RT 20SO Demo Board: Bottom Signal Layer Rev. 1.0 73S8014R/RN/RT 20SO Demo Board User Manual 21 ...
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UM_8014_010 6 Contact Information For more information about Teridian Semiconductor products or to check the availability of the 73S8014R/RN/RT, contact us at: 6440 Oak Canyon Road Suite 100 Irvine, CA 92618-5201 Telephone: (714) 508-8800 FAX: (714) 508-8878 Email: scr.support@teridian.com For ...
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Demo Board User Manual Revision History Revision Date 1.0 7/3/2008 First publication. 24 UM_8014_010 Description Rev. 1.0 ...