73S8014RN-DB Maxim Integrated Products, 73S8014RN-DB Datasheet - Page 9

• Manufacturer Part Number: 73S8014RN-DB
• Description: BOARD DEMO 73S8010RN 20-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of 73S8014RN-DB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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2.1
Keep the CLK signal as short as possible and with few bends in the trace. Keep route of the CLK trace to
one layer (avoid vias to other plane). Keep CLK trace away from other traces especially RST and VCC.
Filtering of the CLK trace is allowed for noise purpose. Up to 30pF to ground is allowed at the CLK pin of
the smart card connector. Also, the 0Ω series resistor, R7, can be replaced for additional filtering (no
more than 100Ω).
Keep the VCC trace as short as possible. Make trace a minimum of 0.5mm thick. Also, keep VCC away
from other traces especially RST and CLK.
Keep RST trace away from VCC and CLK traces. Up to 30pF to ground is allowed for filtering.
Keep 0.1μF close to the VDD pin of the device and directly take other end to ground.
Keep 0.1μF and 10μF close to the VPC pin of the device and directly take other end to ground.
Keep 1.0μF close to the VCC pin of the smart card connector and directly take other end to ground
2.2
Default configuration of the Demo Board contains a 27pF capacitor (C12) from the CLK pin of the smart
connector to ground and a 27pF capacitor (C9) from the RST pin of the smart connector to ground.
These capacitors serve as filters for the CLK and RST signals in the case of long traces or test equipment
perturbations. The capacitor on CLK reduces ringing on the trace, reduces coupling to other traces and
slows down the edge of the CLK signal. The capacitor on RST helps the perturbation specification in a
noisy environment. The filter capacitors can be useful in the EMV test environment and have no effect on
NDS testing
C12 and C9 are represented on both the schematic and BOM. These capacitors are optional filter
capacitors on the smart card lines CLK and RST, respectively for each card interface. These capacitors
may be adjusted (value, not to exceed 30pF) or removed to optimize performance in each specific
application (PCB, card clock frequency, compliance with applicable standards, etc.).
Rev. 1.0
Design Considerations
General Layout Rules
Optimization for Compliance with NDS
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