73S8014RN-DB Maxim Integrated Products, 73S8014RN-DB Datasheet - Page 10

• Manufacturer Part Number: 73S8014RN-DB
• Description: BOARD DEMO 73S8010RN 20-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of 73S8014RN-DB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

73S8014R/RN/RT 20SO Demo Board User Manual
3
3.1
The items described in the following tables refer to the flags in Figure 2.1
10
Item #
(Figure
2.1)
1
2
3
4
5
9
6
7
8
10
11
Use of the Board: Hardware
Board Description: Jumpers, Switches and Test Points
Schemati
c & PCB
Silk-print
Reference
J2
JP3
TP7
TP5
TP3
TP4
J4
TP1
J6
JP1
J5
Board 5V
Board 3.3V
Smart Card
Smart Card
Name
supply and
host digital
interface
VDD Select
Test Points:
CLK
RST
VCC
I/O
supply and
digital control
signals
PIN12
(VDDF_ADJ)
Connector
Clock
selection.
Connector
Table 1: Demo Board Description
Use
Connector that gathers the 5V supply of the board, the
73S8014R/RN/RT data interface (IOUC), external clock (SCLK)
and interrupt (OFF) pins. Note that the external clock (SCLK) can
be left open when JP1 is in position XTAL.
Also note that the 5V power supply pin can be left open when JP2
is in position 3.3V (= support of 3V cards only).
Jumper to select the digital voltage, between 5V or 3.3V This
setting defines the interfacing voltage with the host microcontroller.
It also provides internal supply voltage for internal circuitry to the
73S8014R/RN/RT.
The default setting is in the 3.3V position.
2-pin test points for each respective smart card signal. The pin
label name is the respective signal (i.e. VCC, CLK) and the other
pin is GND.
Connector that gathers the 3.3V supply of the board, the
73S8014R/RN/RT host control signal pins RSTIN, CMDVCC /
CMDVCC%, 5V/#V / CMDVCC#, CLKDIV2 and CLKDIV1.
Note that the 3.3V power supply pin can be left open when JP3 is
in position 5V.
VDD voltage fault adjustment. Pin to the left is connected to the
VDDF_ADJ pin of the 73S8014R/RN/RT and the pin to the right is
GND. When either a resistor R3, or a resistor network R1 and R3
is populated on the board, it adjusts the VDD fault level that
internally triggers a card deactivation sequence.
By default, the resistors R1 and R3 are not connected. It provides
a VDD fault level of 2.3V typical (internally set to the
73S8014R/RN/RT).
Refers to the 73S8014R/RN/RT Data Sheet for further information
about VDD fault level and determination of these resistor values.
SIM/SAM smart card format connector.
Note that J6 is wired is parallel to the smart card connector J5
(underneath the PCB). No SIM/SAM should be inserted when
using the credit-card size connector J5.
Jumper to select between a crystal and external clock as the
frequency reference to the device. The default setting is for a
crystal.
Smart card connector.
When inserting a card (credit card size format), contacts must face
up.
UM_8014_010
Rev. 1.0