73S8014RN-DB Maxim Integrated Products, 73S8014RN-DB Datasheet - Page 17

• Manufacturer Part Number: 73S8014RN-DB
• Description: BOARD DEMO 73S8010RN 20-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of 73S8014RN-DB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM_8014_010
Rev. 1.0
CMDVCCB/CMDVCC5B
5V3VB/CMDVCC3B
J1 and J3 are placed on the bottom.
are placed on the top side.
J1 must be aligned with J2 and J3 must be
aligned with J4 in order for this daughter
board to be stacked on another.
CLKDIV1
CLKDIV2
SSM_110_L_SV
TSM_110_01_L_SV
SSM_110_L_SV
TSM_110_01_L_SV
+3.3V
RSTIN
SCLK
OFFB
GND
GND
GND
+5V
+5V
SIO
GND
J1
10
J2
10
J3
10
J4
10
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
S_C4
S_C8
5.0V
3.3V
C3
C10
J2 and J4
10uF
10uF
Figure 4: TERIDIAN 73S8014R/RN/RT 20SO Demo Board: Electrical Schematic
XTALIN
SELECT
JP1
C5
22pF
When using an external clock
source, C7 should be removed.
C1, C2, C8 and C5 must be
placed within 5mm of the U1
pins and connected by thick
track (wider than 0.5mm)
2
Y1
12.000MHz
1
C4
22pF
CLKDIV1
OFF
RSTIN
I/OUC
CLKDIV2
CMDVCCB/CMDVCC5B
5V3VB/CMDVCC3B
XTALIN
XTALOUT
XTALOUT
XTALOUT
XTALOUT
5.0V
C1
C2
10
U1
1
2
3
4
5
6
7
8
9
73S8014R(N)/RT
OFF
RSTIN
I/OUC
VPC
CLKDIV2
CMDVCC/CMDVCC5
5V_3V/CMDVCC3
GND
XTALIN
XTALOUT
10uF
0.1uF
27pF
C12
I/O
VDD
J5
TP4
Smart Card Connector
VDDF_ADJ
1
2
CLKDIV1
PRES
GND
GND
VCC
VDD
CLK
RST
I/O
20
19
18
17
16
15
14
13
12
11
R1
DNI
R3
DNI
VDD
VDDF_ADJ
73S8014R/RN/RT 20SO Demo Board User Manual
R6
20K
R10
Ru
DNI
R13
Rd
DNI
27pF
PRES
VCC
CLK
RST
IO
VDD
C9
J6
TP1
C6
DNI
1
2
SIM/SAM Connector
R7
0
VDD
1.0uF
C11
C8
0.1uF
TP3
TP5
TP7
1
2
1
2
1
2
5.0V
VCC
RST
CLK
3.3V
R8
Ru
DNI
R11
Rd
DNI
TP3 to TP8 to be placed
very close to the pads
of J5
3.3V
5V
1
2
3
R9
Ru
DNI
R12
Rd
DNI
JP3
VDD
SELECT
R8 to R13 and C36 to be
placed within 1cm of
J7.
17