TDA9898HN/V2,551 NXP Semiconductors, TDA9898HN/V2,551 Datasheet - Page 48

• Manufacturer Part Number: TDA9898HN/V2,551
• Description: IC IF PROCESSOR MULTISTD 48HVQFN
• Manufacturer: NXP Semiconductors

Specifications of TDA9898HN/V2,551

• Function: IF Processor
• Rf Type: ATV, DVB, FM
• Package / Case: 48-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935283079551; TDA9898HN/V2-S; TDA9898HN/V2-S

NXP Semiconductors
Table 53.
V
f
for L); IF input from 50
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of
TDA9897_TDA9898_4
Product data sheet
Symbol
TAGC loop based on VIF AGC (W6[7:6] = 11); TAGC is voltage output; applicable for TV mode: positive modulation and
optional for negative modulation); see
V
V
TOP adjust 2; pin TOP2; IF based TAGC loop mode; see
V
R
R
Pin CTAGC
V
I
R
Pin MPP output characteristic
General
V
V
I
R
SC
L
o(max)
P
acc(set)TOP2
G
i(IF)(RMS)
O
TOP2
CTAGC
sat(u)
sat(l)
I
TOP2
O
O
= 5 V; T
acc(set)TOP2
= 32.875 MHz; PC / SC = 13 dB; f
slip(TAGC)
amb
Characteristics
/ T TOP2 setting accuracy
= 25 C; see
Parameter
RMS IF input voltage
TOP2 setting accuracy
variation with temperature
output voltage
TAGC slip gain offset
voltage on pin TOP2 (DC)
input resistance
resistance on pin TOP2
voltage on pin CTAGC
leakage current
output resistance
upper saturation voltage
lower saturation voltage
maximum output current
output resistance
via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
Table 24
…continued
for input frequencies; B/G standard is used for the specification (f
AF
Table
= 400 Hz); input level V
47,
Conditions
for TOP2; at starting point
of tuner AGC takeover;
V
V
no tuner gain reduction
maximum tuner gain
reduction
tuner gain voltage from
0.6 V to 3.5 V
pin open-circuit
adjustment of VIF AGC
based TAGC loop
sink or source
equivalent time constant
resistance
sink or source
Figure 13
TAGC
TAGC
R
W10[5:0] = 00 0000
R
W10[5:0] = 01 0000
R
W10[5:0] = 01 1111
W10[5] = 1; external
resistor operation
W10[5] = 0; forced
I
2
Rev. 04 — 25 May 2009
TOP2
TOP2
TOP2
C-bus operation
= 3.5 V
= 3.5 V
= 22 k or
= 10 k or
= 0 k
and
Figure 14
Figure 14
i(IF)
= 10 mV (RMS) (sync level for B/G; peak white level
TDA9897; TDA9898
[3]
[3]
[3]
[3]
[3]
Multistandard hybrid IF processing
Min
-
-
-
-
-
4.5
0.2
3
-
-
0
100
0.2
-
-
V
-
350
-
Figure
8
P
0.8 V
51; unless otherwise specified.
Typ
56.9
78.5
98
99
-
0.03
-
-
5
3.5
27
-
-
-
-
10
0.5
-
1.3
P
0.5
PC
© NXP B.V. 2009. All rights reserved.
= 38.375 MHz;
Max
-
-
-
-
+8
0.07
V
0.6
8
-
-
22
-
0.55V
10
-
-
0.8
-
3
P
P
Unit
dB V
dB V
dB V
dB V
dB
dB/K
V
V
dB
V
k
k
k
V
nA
M
V
V
k
48 of 103
A