EM250-RTR Ember, EM250-RTR Datasheet - Page 99

IC ZIGBEE SYSTEM-ON-CHIP 48-QFN

EM250-RTR

Manufacturer Part Number
EM250-RTR
Description
IC ZIGBEE SYSTEM-ON-CHIP 48-QFN
Manufacturer
Ember
Series
EM250r
Datasheet

Specifications of EM250-RTR

Frequency
2.4GHz
Modulation Or Protocol
802.15.4 Zigbee
Applications
Home/Building Automation, Industrial Control and Monitoring
Power - Output
3dBm
Sensitivity
-97dBm
Voltage - Supply
2 V ~ 3.6 V
Current - Receiving
35.5mA
Current - Transmitting
33mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 5kB SRAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
For Use With
636-1009 - PROGRAMMER USB FLASH EM250/260
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Rate - Maximum
-
Other names
636-1000-2

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EM250-RTR
Manufacturer:
TI
Quantity:
3 400
Part Number:
EM250-RTR
Manufacturer:
EMBER
Quantity:
20 000
Company:
Part Number:
EM250-RTR
Quantity:
299
ADC_CFG [0x4902]
ADC_RATE
ADC_SEL
ADC_DITH
ADC_EN
0-R
0-R
15
0
0
7
Table 36 lists the specifications for the ADC.
Parameter
Conversion time
VREF
VREF output current
VREF load capacitance
Minimum input voltage
Maximum input voltage
Single-ended signal range
Differential signal range
Common mode range
Input referred ADC offset
The signal-ended ADC measurements are limited in their range and only guaranteed for accuracy in the range
0 to VREF. The nature of the ADC's internal design allows for measurements outside of this range, but such
measurements are not guaranteed and instead act as a factor of safety. Maximum input voltage, VDD, can be
treated as the failure point. Measurement is not guaranteed at this level, and damage is possible above this
level. The maximum input voltage is of more interest to the differential sampling where a differential meas-
urement might be small, but a common mode can push the actual input voltage on one of the signals towards
VDD.
5.5.1
0-RW
0-R
14
0
6
[14:12]
[11:8]
[1]
[0]
Registers
ADC_RATE
ADC conversion rate selection. Refer to Table 33 for details.
ADC input selection. Refer to Table 34 for details.
Set this bit to disable dither.
Set this bit to enable the ADC.
0-RW
0-R
13
0
5
0-RW
0-R
12
0
4
Table 36. ADC Specifications
0-RW
0-R
11
0
3
0
0
0
- 10
Min.
32
- VREF
0-RW
0-R
10
0
2
ADC_SEL
Typ.
1.2
ADC_DITH
0-RW
0-RW
9
1
Max.
4096
1
10
VDD
VREF
+ VREF
VREF
10
120-0082-000I
EM250
mV
Unit
µs
V
mA
nF
V
V
V
V
V
ADC_EN
0-RW
0-RW
8
0
99

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