MC13213 Freescale Semiconductor, MC13213 Datasheet - Page 15

IC TXRX RF 2.4GHZ FLSH 60K 71LGA

MC13213

Manufacturer Part Number
MC13213
Description
IC TXRX RF 2.4GHZ FLSH 60K 71LGA
Manufacturer
Freescale Semiconductor
Series
MC1321xr
Datasheet

Specifications of MC13213

Frequency
2.4GHz
Data Rate - Maximum
250kbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3dBm
Sensitivity
-92dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
42mA
Current - Transmitting
35mA
Data Interface
PCB, Surface Mount
Memory Size
60kB Flash, 4kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
71-LGA
Number Of Receivers
1
Number Of Transmitters
1
Wireless Frequency
2.4 GHz to 2.48 GHz
Interface Type
SPI
Output Power
0 dBm to 2 dBm
Operating Supply Voltage
2 V to 3.4 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Maximum Supply Current
42 mA
Minimum Operating Temperature
- 40 C
Protocol Supported
802.15.4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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3.2
3.3
Figure 5
Figure 5
(master) initiates all SPI transfers. During a transfer, the master shifts data out (on the MOSI pin) to the
slave while simultaneously shifting data in (on the MISO pin) from the slave. Although the SPI interface
supports simultaneous data exchange between master and slave, the modem SPI protocol only uses data
exchange in one direction at a time. The SPSCK signal is a clock output from the master and an input to
the slave. The slave device must be selected by a low level on the slave select input (SS1 pin).
Freescale Semiconductor
MCU bus master
Modem bus slave
Programmable SPI clock rate; maximum rate is 8 MHz
Double-buffered transmit and receive at MCU
Serial clock phase and polarity must meet modem requirements (MCU control bits
Slave select programmed to meet modem protocol
shows the SPI system level diagram.
shows the SPI modules of the MCU and modem in the master-slave arrangement. The MCU
SPI Features
SPI System Block Diagram
7
6
MCU (MASTER)
GENERATOR
SPI SHIFTER
5
CLOCK
4
3
2
1
0
MC13211/212/213 Technical Data, Rev. 1.8
Figure 5. SPI System Block Diagram
MOS1
MISO1
SPSCK1
PTE2/SS1
SPICLK
MOSI
MISO
CE
MODEM (SLAVE)
7
6
SPI SHIFTER
5
4
3
2
1
0
15

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