TDA5251 Infineon Technologies, TDA5251 Datasheet - Page 35

TXRX FSK/ASK SGL LP TSSOP-38

TDA5251

Manufacturer Part Number
TDA5251
Description
TXRX FSK/ASK SGL LP TSSOP-38
Manufacturer
Infineon Technologies
Type
Transceiverr
Datasheets

Specifications of TDA5251

Package / Case
38-TSSOP
Frequency
315MHz
Data Rate - Maximum
64kbps
Modulation Or Protocol
ASK, FSK
Applications
RKE, Remote Control Systems
Power - Output
13dBm
Sensitivity
-109dBm
Voltage - Supply
2.1 V ~ 5.5 V
Current - Receiving
9.3mA
Current - Transmitting
14mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Operating Frequency
0.35 MHz
Operating Supply Voltage
2.5 V, 3.3 V, 5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Product Depth (mm)
4.4mm
Product Length (mm)
9.7mm
Operating Supply Voltage (min)
2.1V
Operating Supply Voltage (max)
5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Lead Free Status / Rohs Status
Compliant
Other names
SP000014554
TDA5251
TDA5251INTR
TDA5251XT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TDA5251
Manufacturer:
INFINEON
Quantity:
276
Table 2-29
Note: Data are valid 500 µs after the crystal oscillator is enabled (see Figure 2-15 and Figure 2-
16, t CLKSU ).
Table 2-30
Note: As long as default settings are used, there is no clock available at the clock output during
Power Down. It is possible to enable the clock during Power Down by setting CLK_EN (Bit D9) in
the Config Register (00H) to HIGH.
2.4.20
The input of the 6Bit-ADC can be switched between two different sources: the RSSI voltage (default
setting) or a resistor network dividing the Vcc voltage by 5.
Table 2-31
Data Sheet
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SELECT
D5
0
0
1
1
0
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
RSSI and Supply Voltage Measurement
CLK_DIV Output Selection
CLK_DIV Setting
Source for 6Bit-ADC Selection (Register 08H)
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D4
0
1
0
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Total Divider Ratio
Input for 6Bit-ADC
RSSI (default)
Vcc / 5
10
12
14
16
18
20
22
24
26
28
30
32
2
4
6
8
Output from Divider (default)
35
Window Count Complete
13.125MHz
Output
32kHz
Output Frequency [MHz]
0.730 (default)
0.,55
0.94
0.82
0.47
0.44
0.41
Functional Description
0.66
3.3
2.2
1.6
1.3
1.1
0.6
0.5
6.6
TDA5251 F1
Version 1.1
2007-02-26

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