ATMEGA256RZAV-8AU Atmel, ATMEGA256RZAV-8AU Datasheet - Page 186
ATMEGA256RZAV-8AU
Manufacturer Part Number
ATMEGA256RZAV-8AU
Description
MCU ATMEGA2561/AT86RF230 64-TQFP
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA640V-8CU.pdf
(38 pages)
2.ATMEGA640V-8CU.pdf
(444 pages)
3.AT86RF230-ZU.pdf
(98 pages)
Specifications of ATMEGA256RZAV-8AU
Frequency
2.4GHz
Modulation Or Protocol
802.15.4 Zigbee
Applications
ISM, ZigBee™
Power - Output
3dBm
Sensitivity
-101dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
15.5mA
Current - Transmitting
16.5mA
Data Interface
PCB, Surface Mount
Memory Size
256kB Flash, 4kB EEPROM, 8kB RAM
Antenna Connector
PCB, Surface Mount
Package / Case
64-TQFP
Wireless Frequency
2.4 GHz
Interface Type
JTAG, SPI
Output Power
3 dBm
For Use With
ATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Data Rate - Maximum
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
ATmega256
- Current page: 186 of 444
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19.9
2549M–AVR–09/10
Timer/Counter Prescaler
•
Figure 19-12. Prescaler for Timer/Counter2
The clock source for Timer/Counter2 is named clk
system I/O clock clk
clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter
(RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can
then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock
source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal. By set-
ting the EXCLK bit in the ASSR, a 32 KHz external clock can be applied. See
Asynchronous Status Register” on page 192
For Timer/Counter2, the possible prescaled selections are: clk
clk
Setting the PSRASY bit in GTCCR resets the prescaler. This allows the user to operate with a
predictable prescaler.
T2S
During asynchronous operation, the synchronization of the Interrupt Flags for the
asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is therefore
advanced by at least one before the processor can read the timer value causing the setting
of the Interrupt Flag. The Output Compare pin is changed on the timer clock and is not
synchronized to the processor clock.
/128, clk
PSRASY
TOSC1
clk
CS20
CS21
CS22
AS2
I/O
T2S
/256, and clk
IO
. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously
clk
T2S
T2S
ATmega640/1280/1281/2560/2561
/1024. Additionally, clk
Clear
for details.
TIMER/COUNTER2 CLOCK SOURCE
T2S
0
. clk
10-BIT T/C PRESCALER
T2S
T2S
clk
as well as 0 (stop) may be selected.
T2
is by default connected to the main
T2S
/8, clk
T2S
/32, clk
“ASSR –
T2S
/64,
186
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