ATMEGA256RZAV-8AU Atmel, ATMEGA256RZAV-8AU Datasheet - Page 281

• Manufacturer Part Number: ATMEGA256RZAV-8AU
• Description: MCU ATMEGA2561/AT86RF230 64-TQFP
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA256RZAV-8AU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: ISM, ZigBee™
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 15.5mA
• Current - Transmitting: 16.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 256kB Flash, 4kB EEPROM, 8kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 64-TQFP
• Wireless Frequency: 2.4 GHz
• Interface Type: JTAG, SPI
• Output Power: 3 dBm
• For Use With: ATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Data Rate - Maximum: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ATmega256

25.4.1
2549M–AVR–09/10
Differential Channels
Table 25-1.
When using differential channels, certain aspects of the conversion need to be taken into
consideration.
Differential conversions are synchronized to the internal clock CK
clock. This synchronization is done automatically by the ADC interface in such a way that the
sample-and-hold occurs at a specific phase of CK
all single conversions, and the first free running conversion) when CK
same amount of time as a single ended conversion (13 ADC clock cycles from the next pres-
caled clock cycle). A conversion initiated by the user when CK
cycles due to the synchronization mechanism. In Free Running mode, a new conversion is initi-
ated immediately after the previous conversion completes, and since CK
all automatically started (that is, all but the first) Free Running conversions will take 14 ADC
clock cycles.
If differential channels are used and conversions are started by Auto Triggering, the ADC must
be switched off between conversions. When Auto Triggering is used, the ADC prescaler is reset
before the conversion is started. Since the stage is dependent of a stable ADC clock prior to the
conversion, this conversion will not be valid. By disabling and then re-enabling the ADC between
each conversion (writing ADEN in ADCSRA to “0” then to “1”), only extended conversions are
performed. The result from the extended conversions will be valid. See
sion Timing” on page 278
Condition
First conversion
Normal conversions, single ended
Auto Triggered conversions
Normal conversions, differential
ADC Conversion Time
for timing details.
ATmega640/1280/1281/2560/2561
Sample & Hold (Cycles from
Start of Conversion)
1.5/2.5
13.5
ADC2
1.5
2
. A conversion initiated by the user (that is,
ADC2
is high will take 14 ADC clock
ADC2
Conversion Time (Cycles)
“Prescaling and Conver-
ADC2
ADC2
equal to half the ADC
is low will take the
is high at this time,
13/14
13.5
25
13
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