SI4431-B1-FM Silicon Laboratories Inc, SI4431-B1-FM Datasheet - Page 58

• Manufacturer Part Number: SI4431-B1-FM
• Description: IC TXRX 240-930MHZ -8-13DB 20QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4431-B1-FM

• Package / Case: 20-VQFN
• Mfg Application Notes: Transitioning SI4430/31 to Rev B
• Frequency: 240MHz ~ 930MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -121dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Wireless Frequency: 240 MHz to 930 MHz
• Output Power: 13 dBm
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 30 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 4mm
• Product Length (mm): 4mm
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si4430/31/32-B1
8.7. Low Duty Cycle Mode
The Low Duty Cycle Mode is available to automatically wake-up the receiver to check if a valid signal is available.
The basic operation of the low duty cycle mode is demonstrated in the figure below. If a valid preamble or sync
word is not detected the chip will return to sleep mode until the beginning of a new WUT period. If a valid preamble
and sync are detected the receiver on period will be extended for the low duty cycle mode duration (TLDC) to
receive all of the packet. The WUT period must be set in conjunction with the low duty cycle mode duration. The R
value (“Register 14h. Wake-up Timer Period 1”) is shared between the WUT and the TLDC. The ldc[7:0] bits are
located in “Register 19h. Low Duty Cycle Mode Duration.” The time of the TLDC is determined by the formula
below:

R
4
2


TLDC
ldc
7 [
:
] 0
ms
32
.
768
Figure 30. Low Duty Cycle Mode
58
Rev 1.1