XC3S50AN-4TQ144I Xilinx Inc, XC3S50AN-4TQ144I Datasheet - Page 75

• Manufacturer Part Number: XC3S50AN-4TQ144I
• Description: IC FPGA SPARTAN 3AN 144TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S50AN-4TQ144I

• Number Of Logic Elements/cells: 1584
• Number Of Labs/clbs: 176
• Total Ram Bits: 55296
• Number Of I /o: 108
• Number Of Gates: 50000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TQG144: 144-lead Thin Quad Flat Package
The XC3S50AN is available in the 144-lead thin quad flat package, TQG144.
Table 68
pair appear together in the table. The table also shows the pin number for each pin and the pin type (as defined in
The XC3S50AN does not support the address output pins for the Byte-wide Peripheral Interface (BPI) configuration mode.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at:
www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip.
Pinout Table
Table 68: Spartan-3AN TQG144 Pinout
DS557 (v4.1) April 1, 2011
Product Specification
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
lists all the package pins. They are sorted by bank number and then by pin name. Pins that form a differential I/O
IO_0
IO_L01N_0
IO_L01P_0
IO_L02N_0
IO_L02P_0/VREF_0
IO_L03N_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L05N_0
IO_L05P_0
IO_L06N_0/GCLK5
IO_L06P_0/GCLK4
IO_L07N_0/GCLK7
IO_L07P_0/GCLK6
IO_L08N_0/GCLK9
IO_L08P_0/GCLK8
IO_L09N_0/GCLK11
IO_L09P_0/GCLK10
IO_L10N_0
IO_L10P_0
IO_L11N_0
IO_L11P_0
IO_L12N_0/PUDC_B
IO_L12P_0/VREF_0
IP_0
IP_0/VREF_0
VCCO_0
VCCO_0
IO_1
IO_L01N_1/LDC2
IO_L01P_1/HDC
IO_L02N_1/LDC0
Pin Name
P142
P111
P110
P113
P112
P117
P115
P116
P114
P121
P120
P126
P124
P127
P125
P131
P129
P132
P130
P135
P134
P139
P138
P143
P141
P140
P123
P119
P136
P79
P78
P76
P77
Pin
INPUT
VCCO
VCCO
VREF
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
VREF
VREF
DUAL
DUAL
DUAL
DUAL
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
www.xilinx.com
Table 68: Spartan-3AN TQG144 Pinout (Cont’d)
Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
Spartan-3AN FPGA Family: Pinout Descriptions
IO_L02P_1/LDC1
IO_L03N_1
IO_L03P_1
IO_L04N_1/RHCLK1
IO_L04P_1/RHCLK0
IO_L05N_1/TRDY1/RHCLK3
IO_L05P_1/RHCLK2
IO_L06N_1/RHCLK5
IO_L06P_1/RHCLK4
IO_L07N_1/RHCLK7
IO_L07P_1/IRDY1/RHCLK6
IO_L08N_1
IO_L08P_1
IO_L09N_1
IO_L09P_1
IO_L10N_1
IO_L10P_1
IO_L11N_1
IO_L11P_1
IP_1/VREF_1
IP_1/VREF_1
VCCO_1
VCCO_1
IO_2/MOSI/CSI_B
IO_L01N_2/M0
IO_L01P_2/M1
IO_L02N_2/CSO_B
IO_L02P_2/M2
IO_L03N_2/VS1
IO_L03P_2/RDWR_B
IO_L04N_2/VS0
IO_L04P_2/VS2
IO_L05N_2/D7
Pin Name
P101
P104
P102
P105
P103
P75
P84
P82
P85
P83
P88
P87
P92
P90
P93
P91
P98
P96
P99
P80
P97
P86
P95
P62
P38
P37
P41
P39
P44
P42
P45
P43
P48
Pin
Table
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
VCCO
VCCO
VREF
VREF
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
62).
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