XC3S50AN-4TQ144I Xilinx Inc, XC3S50AN-4TQ144I Datasheet - Page 79

• Manufacturer Part Number: XC3S50AN-4TQ144I
• Description: IC FPGA SPARTAN 3AN 144TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S50AN-4TQ144I

• Number Of Logic Elements/cells: 1584
• Number Of Labs/clbs: 176
• Total Ram Bits: 55296
• Number Of I /o: 108
• Number Of Gates: 50000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

FTG256: 256-Ball Fine-Pitch, Thin Ball Grid Array
The 256-ball fine-pitch, thin ball grid array package, FTG256, supports the XC3S50AN, XC3S200AN, and XC3S400AN
devices.
the largest device. Pins that form a differential I/O pair appear together in the table. The differential I/O pairs that have
different assignments between the XC3S50AN and the XC3S200AN or XC3S400AN are highlighted in light blue in
See
and the pin type (as defined in
The footprints for the XC3S200AN and XC3S400AN in the FTG256 are identical.
the XC3S200AN and XC3S400AN. The XC3S50AN footprint is compatible with the XC3S200AN and XC3S400AN,
however, there are 51 unconnected balls (indicated as N.C. in
Table 73
The XC3S50AN does not support the address output pins for the byte-wide peripheral interface (BPI) configuration mode.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at:
www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip.
Pinout Table
Table 70: Spartan-3AN FTG256 Pinout (XC3S50AN, XC3S200AN, XC3S400AN)
DS557 (v4.1) April 1, 2011
Product Specification
Footprint Migration Differences, page 87
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 70
summarizes the XC3S50AN FPGA footprint migration differences for the FTG256 package.
IO_L01N_0
IO_L01P_0
IO_L02N_0
IO_L02P_0/VREF_0
IO_L03N_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
N.C.
IP_0
N.C.
N.C.
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
IO_L09N_0/GCLK5
IO_L09P_0/GCLK4
IO_L10N_0/GCLK7
IO_L10P_0/GCLK6
IO_L11N_0/GCLK9
IO_L11P_0/GCLK8
IO_L12N_0/GCLK11
IO_L12P_0/GCLK10
N.C.
N.C.
lists all the package pins for these devices. They are sorted by bank number and then by the pin name of
XC3S50AN Pin Name
Table
62).
for additional information. The table also shows the pin number for each pin
www.xilinx.com
IO_L01N_0
IO_L01P_0
IO_L02N_0
IO_L02P_0/VREF_0
IO_L03N_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L05N_0
IO_L05P_0
IO_L06N_0/VREF_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
IO_L09N_0/GCLK5
IO_L09P_0/GCLK4
IO_L10N_0/GCLK7
IO_L10P_0/GCLK6
IO_L11N_0/GCLK9
IO_L11P_0/GCLK8
IO_L12N_0/GCLK11
IO_L12P_0/GCLK10
IO_L13N_0
IO_L13P_0
XC3S200AN/XC3S400AN Pin Name
Table
70).
Spartan-3AN FPGA Family: Pinout Descriptions
Figure 21
shows the common footprint for
FTG256 Ball
C13
D13
D11
C12
D10
C11
C10
B14
B15
A13
A14
A12
B12
E10
A11
A10
B10
D9
C9
D8
C8
A9
B8
A8
C7
A7
Table
VREF
VREF
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
70.
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