XC3S200AN-4FT256I Xilinx Inc, XC3S200AN-4FT256I Datasheet - Page 100

• Manufacturer Part Number: XC3S200AN-4FT256I
• Description: IC FPGA SPARTAN 3AN 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S200AN-4FT256I

• Number Of Logic Elements/cells: 4032
• Number Of Labs/clbs: 448
• Total Ram Bits: 294912
• Number Of I /o: 195
• Number Of Gates: 200000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

FGG484: 484-Ball Fine-Pitch Ball Grid Array
The 484-ball fine-pitch ball grid array, FGG484, supports both the XC3S700AN and the XC3S1400AN FPGAs. There are
three pinout differences, as described in
Table 78
differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type (as
defined in
The shaded rows indicate pinout differences between the XC3S700AN and the XC3S1400AN FPGAs. The XC3S700AN
has three unconnected balls, indicated as N.C. and with a black diamond (
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at:
www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip.
Pinout Table
Table 78: Spartan-3AN FGG484 Pinout
DS557 (v4.1) April 1, 2011
Product Specification
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
lists all the FGG484 package pins. They are sorted by bank number and then by pin name. Pins that form a
Table
IO_L01N_0
IO_L01P_0
IO_L02N_0
IO_L02P_0/VREF_0
IO_L03N_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L05N_0
IO_L05P_0
IO_L06N_0
IO_L06P_0/VREF_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
IO_L09N_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L11N_0
IO_L11P_0
IO_L12N_0/VREF_0
IO_L12P_0
IO_L13N_0
IO_L13P_0
IO_L14N_0
IO_L14P_0
62).
Pin Name
FGG484
Ball
D18
E17
C19
D19
A20
B20
E15
A18
C18
A19
B19
C17
D17
C16
D16
E14
C14
A17
B17
C15
D15
A15
A16
A14
B15
E13
F15
F13
Table
81.
VREF
VREF
VREF
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
www.xilinx.com
Table 78: Spartan-3AN FGG484 Pinout (Cont’d)
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Spartan-3AN FPGA Family: Pinout Descriptions
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
IO_L17N_0/GCLK5
IO_L17P_0/GCLK4
IO_L18N_0/GCLK7
IO_L18P_0/GCLK6
IO_L19N_0/GCLK9
IO_L19P_0/GCLK8
IO_L20N_0/GCLK11
IO_L20P_0/GCLK10
IO_L21N_0
IO_L21P_0
IO_L22N_0
IO_L22P_0
IO_L23N_0
IO_L23P_0
IO_L24N_0/VREF_0
IO_L24P_0
IO_L25N_0
IO_L25P_0
IO_L26N_0
IO_L26P_0
IO_L27N_0
IO_L27P_0
IO_L28N_0
IO_L28P_0
◆
) in
Table 78
Pin Name
and
Figure
23.
FGG484
Ball
C13
D13
A13
B13
E12
C12
A11
A12
C11
B11
E11
D11
C10
A10
E10
D10
A8
A9
C9
B9
C8
B8
A6
A7
C7
D7
A5
B6
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
VREF
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
100