XC3S200AN-4FT256I Xilinx Inc, XC3S200AN-4FT256I Datasheet - Page 55

• Manufacturer Part Number: XC3S200AN-4FT256I
• Description: IC FPGA SPARTAN 3AN 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S200AN-4FT256I

• Number Of Logic Elements/cells: 4032
• Number Of Labs/clbs: 448
• Total Ram Bits: 294912
• Number Of I /o: 195
• Number Of Gates: 200000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 42: Switching Characteristics for the DFS
DS557 (v4.1) April 1, 2011
Product Specification
CLKOUT_DUTY_CYCLE_FX
Notes:
1.
2.
3.
4.
5.
Output Frequency Ranges
CLKOUT_FREQ_FX
Output Clock Jitter
CLKOUT_PER_JITT_FX
Duty Cycle
Phase Alignment
CLKOUT_PHASE_FX
CLKOUT_PHASE_FX180 Phase offset between the DFS
Lock Time
LOCK_FX
The numbers in this table are based on the operating conditions set forth in
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
Maximum output jitter is characterized within a reasonable noise environment (40 SSOs and 25% CLB switching) on an XC3S1400A FPGA.
Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching
activities, switching frequency, power supply and PCB design. The actual maximum output jitter depends on the system application.
The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, the data sheet specifies a
maximum CLKFX jitter of “±[1% of CLKFX period + 200]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period
is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 200 ps] = ±300 ps.
Symbol
(2)
(4)(5)
(5)
(2)(3)
Frequency for the CLKFX and CLKFX180 outputs
Period jitter at the CLKFX and
CLKFX180 outputs.
Duty cycle precision for the CLKFX and CLKFX180
outputs, including the BUFGMUX and clock tree
duty-cycle distortion
Phase offset between the DFS CLKFX
output and the DLL CLK0 output when
both the DFS and DLL are used
CLKFX180 output and the DLL CLK0
output when both the DFS and DLL
are used
The time from deassertion at the
DCM’s Reset input to the rising
transition at its LOCKED output. The
DFS asserts LOCKED when the
CLKFX and CLKFX180 signals are
valid. If using both the DLL and the
DFS, use the longer locking time.
Description
www.xilinx.com
Spartan-3AN FPGA Family: DC and Switching Characteristics
5 MHz < F
> 20 MHz
< 15 MHz

F
15 MHz
CLKIN
CLKIN
20 MHz
CLKIN
Table 10
CLKIN
>
Device
and
All
All
All
All
All
All
Table
±[1% of
www.xilinx.com/support/documenta
CLKFX
tion/data_sheets/s3a_jitter_calc.zip
period
+ 100]
Min
Typ
41.
5
–
–
–
–
–
Use the Spartan-3A Jitter
-5
±[1% of
±[1% of
±[1% of
CLKFX
CLKFX
CLKFX
period
+ 200]
period
+ 350]
period
+ 200]
±200
Speed Grade
Max
Max
350
450
Calculator:
5
±[1% of
CLKFX
period
+ 100]
Min
Typ
5
–
–
–
–
–
-4
±[1% of
±[1% of
±[1% of
CLKFX
CLKFX
CLKFX
period
+ 200]
period
+ 350]
period
+ 200]
±200
Max
Max
320
450
5
Units
MHz
ms
ps
ps
ps
ps
ps
µs
55