XC3S200AN-4FT256I Xilinx Inc, XC3S200AN-4FT256I Datasheet - Page 121
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XC3S200AN-4FT256I
Manufacturer Part Number
XC3S200AN-4FT256I
Description
IC FPGA SPARTAN 3AN 256FTBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr
Datasheet
1.XC3S50AN-4TQG144C.pdf
(123 pages)
Specifications of XC3S200AN-4FT256I
Number Of Logic Elements/cells
4032
Number Of Labs/clbs
448
Total Ram Bits
294912
Number Of I /o
195
Number Of Gates
200000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-LBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S200AN-4FT256I
Manufacturer:
MOLEX
Quantity:
2 000
Company:
Part Number:
XC3S200AN-4FT256I
Manufacturer:
XILINX
Quantity:
5 142
Company:
Part Number:
XC3S200AN-4FT256I
Manufacturer:
XILINX
Quantity:
290
Company:
Part Number:
XC3S200AN-4FT256I
Manufacturer:
Xilinx Inc
Quantity:
10 000
DS557 (v4.1) April 1, 2011
Product Specification
VCCINT
VCCINT
VCCINT VCCINT
VCCINT
VCCAUX
VCCO_2
INPUT
VREF_0
INPUT
L26N_0
GCLK7
L26P_0
GCLK6
L24P_0
L24N_0
L25N_0
GCLK5
L25P_0
GCLK4
L31P_2
L27P_2
GCLK0
L27N_2
GCLK1
L29N_2
L29P_2
L28N_2
GCLK3
L28P_2
GCLK2
GND
GND
GND
GND
GND
14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCINT
VCCINT
VCCINT
VREF_0
VREF_2
L23N_0
L23P_0
L22N_0
INPUT
L20N_0
L20P_0
L16P_0
L16N_0
INPUT
L35N_2
L35P_2
L31N_2
L34N_2
L34P_2
L30N_2
L30P_2
L32P_2
AWAKE
L32N_2
INPUT
INIT_B
CSI_B
GND
GND
GND
DOUT
MOSI
15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D3
VCCINT
VCCINT
VCCINT
VCCAUX
VCCO_0
VCCO_0
VCCO_2
VCCO_2
INPUT
INPUT
VREF_2
INPUT
L21N_0
L22P_0
L12P_0
L12N_0
L42N_2
L42P_2
L38N_2
L38P_2
GND
GND
GND
GND
GND
GND
GND
16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCINT
VCCAUX
VREF_0
VREF_2
INPUT
L19N_0
L19P_0
L21P_0
L13N_0
L13P_0
L08N_0
L08P_0
INPUT
L55N_1
L39N_1
L27N_1
L17N_1
L46N_2
L46P_2
L43N_2
L43P_2
INPUT
INPUT
L33N_2
L33P_2
INPUT
GND
GND
17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A7
VCCAUX
RHCLK6
INPUT
INPUT
INPUT
L18N_0
L18P_0
L17N_0
L17P_0
L57N_1
L55P_1
L47N_1
L39P_1
L34P_1
L27P_1
L17P_1
L12N_1
L08P_1
L47N_2
L47P_2
L36N_2
L36P_2
IRDY1
GND
N.C.
N.C.
N.C.
N.C.
A14
18
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A6
D1
D2
Bank 0
VCCO_0
VCCO_1
RHCLK7
VCCO_1
VCCO_2
VREF_0
L15N_0
L15P_0
INPUT
L02N_0
L02P_0
L59P_1
L57P_1
L47P_1
L34N_1
L22P_1
L12P_1
L08N_1
INPUT
L40N_2
L40P_2
L37N_2
L37P_2
GND
GND
GND
GND
N.C.
19
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Bank 2
VREF_0
RHCLK1
VREF_2
INPUT
INPUT
INPUT
L14N_0
L14P_0
L11N_0
L11P_0
L01N_0
L01P_0
L64P_1
L59N_1
L53N_1
L53P_1
L42N_1
L42P_1
L30N_1
L22N_1
L14N_1
L10N_1
L04P_1
L01P_1
L41N_2
L41P_2
L39N_2
L39P_2
HDC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A24
I/O
I/O
I/O
I/O
A17
I/O
A16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
20
Figure 24: FGG676 Package Footprint (Top View)
RHCLK0
L09N_0
L09P_0
L10N_0
L10P_0
L64N_1
L62N_1
L62P_1
L50N_1
L45P_1
L37N_1
L30P_1
L25P_1
L14P_1
L10P_1
L04N_1
L01N_1
DONE
L45N_2
L44N_2
L44P_2
GND
GND
GND
GND
GND
GND
LDC2
A25
A21
A20
21
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A2
VCCAUX
VCCAUX
VCCAUX
VCCO_0
VREF_1
VCCO_1
VCCO_1
VCCO_1
VCCO_2
VREF_2
INPUT
L07N_0
L05N_0
L05P_0
L58P_1
L58N_1
L49N_1
L46N_1
L50P_1
L45N_1
L37P_1
L25N_1
L21N_1
L18N_1
L13P_1
L09P_1
L45P_2
N.C.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
22
A3
RHCLK4
VREF_1
INPUT
L07P_0
L06N_0
L06P_0
L56N_1
L51P_1
INPUT
L48P_1
L49P_1
L46P_1
INPUT
L40N_1
L38N_1
INPUT
L36N_1
L33P_1
INPUT
L28P_1
L26P_1
L23P_1
L21P_1
L18P_1
L13N_1
L09N_1
L07P_1
L03P_1
L48N_2
L48P_2
TDO
N.C.
A13
23
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A4
A0
DIN/MISO
VREF_1
RHCLK5
VREF_1
VREF_1
www.xilinx.com
INPUT
INPUT
INPUT
INPUT
L61N_1
L56P_1
L54N_1
L51N_1
L48N_1
L40P_1
L38P_1
L36P_1
L33N_1
L28N_1
L26N_1
L23N_1
L19P_1
L15P_1
L11P_1
L07N_1
L03N_1
L52N_2
L52P_2
N.C.
N.C.
GND
GND
GND
GND
GND
CCLK
I/O
I/O
I/O
I/O
I/O
A12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
24
A5
A1
D0
VCCO_1
VCCO_1
RHCLK 3
VCCO_1
VCCO_1
VREF_1
INPUT
L65N_1
L63N_1
L61P_1
L54P_1
INPUT
L52N_1
INPUT
L44N_1
L43N_1
L41P_1
L35N_1
INPUT
L32N_1
L31N_1
L29P_1
INPUT
L24P_1
L19N_1
INPUT
L16P_1
L15N_1
L11N_1
L05N_1
L02N_1
L51N_2
L51P_2
TRDY1
TCK
LDC0
A23
A19
A11
25
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A8
DS557-4_08_030911
VREF_1
VREF_1
RHCLK2
VREF_1
VREF_1
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
L65P_1
L63P_1
L60N_1
L60P_1
L52P_1
L44P_1
L43P_1
L41N_1
L35P_1
L32P_1
L31P_1
L29N_1
L24N_1
L20N_1
L20P_1
L16N_1
L06N_1
L06P_1
L05P_1
L02P_1
GND
GND
GND
GND
GND
GND
LDC1
26
I/O
A22
I/O
I/O
I/O
A18
I/O
I/O
A10
I/O
I/O
I/O
I/O
I/O
I/O
A9
G
M
W
A
B
C
D
E
F
H
J
K
L
N
P
R
T
U
V
Y
A
A
A
B
A
C
A
D
A
E
A
F
Spartan-3AN FPGA Family: Pinout Descriptions
Right Half of FGG676
Package (Top View)
121