ATMEGA64A-MNR Atmel, ATMEGA64A-MNR Datasheet - Page 111

IC MCU AVR 64K FLASH 8QFN

ATMEGA64A-MNR

Manufacturer Part Number
ATMEGA64A-MNR
Description
IC MCU AVR 64K FLASH 8QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet

Specifications of ATMEGA64A-MNR

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI, UART, I2C
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
ATMEGA64A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
15. 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
15.1
15.1.1
15.2
8160C–AVR–07/09
Features
Overview
Restrictions in ATmega103 Compatibility Mode
Note that in ATmega103 compatibility mode, only one 16-bit Timer/Counter is available
(Timer/Counter1). Also note that in ATmega103 compatibility mode, the Timer/Counter1 has two
compare registers (Compare A and Compare B) only.
The 16-bit Timer/Counter unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement. Most register and bit references in this
datasheet are written in general form. A lower case “n” replaces the Timer/Counter number, and
a lower case “x” replaces the Output Compare unit channel. However, when using the register or
bit defines in a program, the precise form must be used (i.e,. TCNT1 for accessing
Timer/Counter1 counter value and so on). The physical I/O Register and bit locations for
ATmega64A are listed in the
A simplified block diagram of the 16-bit Timer/Counter is shown in
I/O Registers, including I/O bits and I/O pins, are shown in bold.
True 16-bit Design (i.e., Allows 16-bit PWM)
Three Independent Output Compare Units
Double Buffered Output Compare Registers
One Input Capture Unit
Input Capture Noise Canceler
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Variable PWM Period
Frequency Generator
External Event Counter
Ten Independent Interrupt Sources (TOV1, OCF1A, OCF1B, OCF1C, ICF1, TOV3, OCF3A, OCF3B,
OCF3C, and ICF3)
“16-bit Timer/Counter Register Description” on page
Figure
ATmega64A
15-1. CPU accessible
133.
111

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