ATMEGA64A-MNR Atmel, ATMEGA64A-MNR Datasheet - Page 26
ATMEGA64A-MNR
Manufacturer Part Number
ATMEGA64A-MNR
Description
IC MCU AVR 64K FLASH 8QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA64A-AU.pdf
(392 pages)
Specifications of ATMEGA64A-MNR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI, UART, I2C
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
ATMEGA64A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8160C–AVR–07/09
Note that the XMEM interface is asynchronous and that the waveforms in the following figures
are related to the internal system clock. The skew between the internal and external clock
(XTAL1) is not guaranteed (varies between devices, temperature, and supply voltage). Conse-
quently the XMEM interface is not suited for synchronous operation.
Figure 7-6.
Note:
Figure 7-7.
Note:
System Clock (CLK
System Clock (CLK
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
SRW00 (lower sector).
The ALE pulse in period T4 is only present if the next instruction accesses the RAM (internal
or external).
SRW00 (lower sector).
The ALE pulse in period T5 is only present if the next instruction accesses the RAM (internal
or external).
External Data Memory Cycles without Wait State
(SRWn1 = 0 and SRWn0 =0)
External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1
DA7:0
A15:8
CPU
ALE
DA7:0
WR
A15:8
RD
CPU
ALE
WR
)
RD
)
Prev. Addr.
Prev. Data
Prev. Data
Prev. Data
Prev. addr.
Prev. data
Prev. data
Prev. data
T1
T1
Address
Address
Address
T2
Address
Address
Address
XX
T2
XX
XXXXX
Address
T3
Data
Data
Data
Address
T3
Data
Data
Data
(1)
T4
ATmega64A
XXXXXXXX
T4
T5
(1)
26
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