ATMEGA64A-MNR Atmel, ATMEGA64A-MNR Datasheet - Page 25

• Manufacturer Part Number: ATMEGA64A-MNR
• Description: IC MCU AVR 64K FLASH 8QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64A-MNR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, UART, I2C
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: ATMEGA64A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5.5
7.5.6
8160C–AVR–07/09
Pull-up and Bus Keeper
Timing
The external memory interface is designed to guaranty minimum address hold time after G is
asserted low of t
The D to Q propagation delay (t
time requirement of the external component. The data setup time before G low (t
exceed address valid to ALE low (t
load).
Figure 7-5.
The pull-ups on the AD7:0 ports may be activated if the corresponding Port Register is written to
one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by
writing the Port Register to zero before entering sleep.
The XMEM interface also provides a Bus Keeper on the AD7:0 lines. The Bus Keeper can be
disabled and enabled in software as described in
B” on page
the AD7:0 bus when these lines would otherwise be tri-stated by the XMEM interface.
External memory devices have different timing requirements. To meet these requirements, the
ATmega64A XMEM interface provides four different wait states as shown in
important to consider the timing specification of the external memory device before selecting the
wait-state. The most important parameters are the access time for the external memory com-
pared to the set-up requirement of the ATmega64A. The access time for the external memory is
defined to be the time from receiving the chip select/address until the data of this address actu-
ally is driven on the bus. The access time cannot exceed the time from the ALE pulse is asserted
low until data must be stable during a read sequence (t
28-15 on page
is possible to divide the external memory space in two sectors with individual wait-state settings.
This makes it possible to connect two different memory devices with different timing require-
ments to the same XMEM interface. For XMEM interface timing details, please refer to
28-6
• D to Q propagation delay (t
• Data setup time before G low (t
• Data (address) hold time after G low (
to
Figure
32. When enabled, the Bus Keeper will ensure a defined logic level (zero or one) on
External SRAM Connected to the AVR
28-9, and
340). The different wait states are set up in software. As an additional feature, it
h
AVR
= 5 ns (refer to t
AD7:0
A15:8
ALE
WR
RD
Table 28-8
pd
pd
).
) must be taken into consideration when calculating the access
su
LAXX_LD
AVLLC
).
to
Table
) minus PCB wiring delay (dependent on the capacitive
th
/t
).
LLAXX_ST
D
G
28-15.
“XMCRB – External Memory Control Register
Q
in
Table 28-8
LLRL
+ t
RLRH
to
- t
D[7:0]
A[15:8]
A[7:0]
RD
WR
DVRH
Table 28-15 on page
SRAM
ATmega64A
in
Table 28-8
Table
su
) must not
7-3. It is
to
Figure
Table
340).
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