ATMEGA64A-MNR Atmel, ATMEGA64A-MNR Datasheet - Page 178
ATMEGA64A-MNR
Manufacturer Part Number
ATMEGA64A-MNR
Description
IC MCU AVR 64K FLASH 8QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA64A-AU.pdf
(392 pages)
Specifications of ATMEGA64A-MNR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI, UART, I2C
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
ATMEGA64A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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20.3.3
20.3.4
20.4
8160C–AVR–07/09
Frame Formats
External Clock
Synchronous Clock Operation
External clocking is used by the synchronous slave modes of operation. The description in this
section refers to
External clock input from the XCK pin is sampled by a synchronization register to minimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector before it can be used by the Transmitter and Receiver. This process intro-
duces a two CPU clock period delay and therefore the maximum external XCK clock frequency
is limited by the following equation:
Note that f
add some margin to avoid possible loss of data due to frequency variations.
When synchronous mode is used (UMSELn = 1), the XCK pin will be used as either clock input
(Slave) or clock output (Master). The dependency between the clock edges and data sampling
or data change is the same. The basic principle is that data input (on RxD) is sampled at the
opposite XCK clock edge of the edge the data output (TxD) is changed.
Figure 20-3. Synchronous Mode XCK Timing
The UCPOLn bit UCRSnC selects which XCK clock edge is used for data sampling and which is
used for data change. As
rising XCK edge and sampled at falling XCK edge. If UCPOLn is set, the data will be changed at
falling XCK edge and sampled at rising XCK edge.
A serial frame is defined to be one character of data bits with synchronization bits (start and stop
bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of
the following as valid frame formats:
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, even or odd parity bit
• 1 or 2 stop bits
UCPOLn = 1
UCPOLn = 0
osc
depends on the stability of the system clock source. It is therefore recommended to
Figure 20-2
RxD / TxD
RxD / TxD
XCK
XCK
Figure 20-3
for details.
shows, when UCPOLn is zero the data will be changed at
f
XCK
<
f
---------- -
OSC
4
Sample
Sample
ATmega64A
178
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