PK30X256VMD100 Freescale Semiconductor, PK30X256VMD100 Datasheet - Page 22

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PK30X256VMD100

Manufacturer Part Number
PK30X256VMD100
Description
IC ARM CORTEX MCU 256K 144-MAP
Manufacturer
Freescale Semiconductor
Series
Kinetisr
Datasheets

Specifications of PK30X256VMD100

Core Processor
ARM Cortex-M4
Core Size
32-Bit
Speed
100MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART
Peripherals
DMA, I²S, LCD, LVD, POR, PWM, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 3.6 V
Data Converters
A/D 37x16b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LBGA
Rohs Compliant
Yes
Processor Series
Kinetis
Core
ARM Cortex M4
Data Ram Size
64 KB
Interface Type
UART, SPI, I2C, I2S, CAN
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
102
Operating Supply Voltage
1.71 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PK30X256VMD100
Manufacturer:
FSL
Quantity:
10
Part Number:
PK30X256VMD100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Peripheral operating requirements and behaviors
22
Symbol
Symbol
J10
J11
J12
J13
J14
J3
J4
J5
J6
J7
J8
J9
J1
J2
J3
J4
J5
J6
J7
J8
J9
TCLK clock pulse width
TCLK rise and fall times
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
Operating voltage
TCLK frequency of operation
TCLK cycle period
TCLK clock pulse width
TCLK rise and fall times
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
Description
Description
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
Table 11. JTAG limited voltage range electricals (continued)
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Table 12. JTAG full voltage range electricals
Table continues on the next page...
Preliminary
1.71
1/J1
12.5
Min.
Min.
100
50
20
10
20
50
25
20
0
8
1
8
0
0
0
0
8
Freescale Semiconductor, Inc.
Max.
Max.
3.6
25
25
17
17
10
20
40
25
25
3
3
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V

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