PK30X256VMD100 Freescale Semiconductor, PK30X256VMD100 Datasheet - Page 45
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PK30X256VMD100
Manufacturer Part Number
PK30X256VMD100
Description
IC ARM CORTEX MCU 256K 144-MAP
Manufacturer
Freescale Semiconductor
Series
Kinetisr
Specifications of PK30X256VMD100
Core Processor
ARM Cortex-M4
Core Size
32-Bit
Speed
100MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART
Peripherals
DMA, I²S, LCD, LVD, POR, PWM, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 3.6 V
Data Converters
A/D 37x16b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LBGA
Rohs Compliant
Yes
Processor Series
Kinetis
Core
ARM Cortex M4
Data Ram Size
64 KB
Interface Type
UART, SPI, I2C, I2S, CAN
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
102
Operating Supply Voltage
1.71 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PK30X256VMD100
Manufacturer:
FSL
Quantity:
10
Company:
Part Number:
PK30X256VMD100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
1. Typical values assume V
2. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
3. This is the input leakage current of the module in addition to the PAD leakage current.
4. Gain = 2
5. When the PGA gain is changed, it takes some time to settle the output for the ADC to work properly. During a gain
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
6.6.2 CMP and 6-bit DAC electrical specifications
Freescale Semiconductor, Inc.
Symbol
SINAD
Symbol
ENOB
function if input common mode voltage (V
switching, a few ADC outputs should be discarded (minimum two data samples, may be more depending on ADC
sampling rate and time of the switching).
PGA reference voltage and gain setting.
I
I
V
V
V
DDHS
DDLS
AIN
AIO
DD
PGAG
Effective number
of bits
Signal-to-noise
plus distortion
ratio
Description
Supply voltage
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
Analog input offset voltage
Description
Table 28. Comparator and 6-bit DAC electrical specifications
Table 27. 16-bit ADC with PGA characteristics (continued)
DDA
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
=3.0V, Temp=25°C, f
See ENOB
Conditions
• Gain=1, Average=4
• Gain=1, Average=8
• Gain=64, Average=4
• Gain=64, Average=8
• Gain=1, Average=32
• Gain=2, Average=32
• Gain=4, Average=32
• Gain=8, Average=32
• Gain=16, Average=32
• Gain=32, Average=32
• Gain=64, Average=32
CM
Table continues on the next page...
) and the PGA gain.
ADCK
Preliminary
=6MHz unless otherwise stated.
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Min.
6.02 × ENOB + 1.76
V
Peripheral operating requirements and behaviors
SS
1.71
Min.
—
—
—
– 0.3
Typ.
12.3
12.7
13.3
13.1
12.5
11.8
11.1
10.2
8.4
8.7
9.3
1
Typ.
—
—
—
—
—
Max.
—
—
—
—
—
—
—
—
—
—
—
Unit
bits
bits
bits
bits
bits
bits
bits
bits
bits
bits
bits
dB
Max.
V
200
3.6
20
20
DD
differential
f
in
mode,
Notes
=500Hz
16-bit
Unit
mV
μA
μA
V
V
45