UJA1079ATW/3V3/WD, NXP Semiconductors, UJA1079ATW/3V3/WD, Datasheet - Page 37

• Manufacturer Part Number: UJA1079ATW/3V3/WD,
• Description: IC SBC LIN 3.3V 32HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1079ATW/3V3/WD,

• Controller Type: System Basis Chip
• Interface: SPI
• Voltage - Supply: 4.5 V ~ 28 V
• Current - Supply: 75µA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
[3]
[4]
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UJA1079A
Product data sheet
Fig 16. LIN transceiver timing diagram
output of receiving
output of receiving
t
A system reset will be performed if the watchdog is in Window mode and is triggered less than t
period (or in the first half of the watchdog period).
The nominal watchdog period is programmed via the NWP control bits in the WD_and_Status register (see
Window mode only.
The watchdog will be reset if it is in window mode and is triggered at least t
watchdog period (or in the second half of the watchdog period). A system reset will be performed if the watchdog is triggered more than
t
δ2 δ4
PD(RX)sym
trig(wd)2
LIN bus signal
,
after the start of the watchdog period (watchdog overflows).
=
node A
node B
V
= t
V
t
------------------------------- -
TXDL
bus rec
BAT
PD(RX)r
2 t
(
×
V
V
) max
bit
RXDL
RXDL
(
− t
PD(RX)f
)
Fig 15. Timing test circuit for LIN transceiver
.
.
t
t
PD(RX)f
bit
All information provided in this document is subject to legal disclaimers.
C
t
t
bus(dom)(max)
bus(dom)(min)
RXDL
Rev. 2 — 31 January 2011
t
PD(RX)r
t
bit
t
PD(RX)r
RXDL
TXDL
t
t
bus(rec)(min)
bus(rec)(max)
trig(wd)1
SBC
GND
BAT
t
, but not more than t
bit
DLIN
LIN
t
PD(RX)f
trig(wd)1
015aaa133
LIN core system basis chip
V
V
V
V
th(rec)RX(max)
th(dom)RX(max)
th(rec)RX(min)
th(dom)RX(min)
trig(wd)2
after the start of the watchdog
015aaa204
UJA1079A
Table
, after the start of the
R
C
LIN
© NXP B.V. 2011. All rights reserved.
LIN
4); valid in watchdog
thresholds of
receiving node A
thresholds of
receiving node B
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