UJA1079ATW/3V3/WD, NXP Semiconductors, UJA1079ATW/3V3/WD, Datasheet - Page 9

• Manufacturer Part Number: UJA1079ATW/3V3/WD,
• Description: IC SBC LIN 3.3V 32HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1079ATW/3V3/WD,

• Controller Type: System Basis Chip
• Interface: SPI
• Voltage - Supply: 4.5 V ~ 28 V
• Current - Supply: 75µA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
UJA1079A
Product data sheet
6.1.2 Off mode
6.1.3 Standby mode
6.1.4 Normal mode
The SBC switches to Off mode from all other modes if the battery supply drops below the
power-off detection threshold (V
and the bus system is in a high-resistive state.
As soon as the battery supply rises above the power-on detection threshold (V
the SBC goes to Standby mode, and a system reset is executed (reset pulse width of
t
The SBC will enter Standby mode:
In Standby mode, V1 is switched on. The LIN transceiver will either be in a low-power
state (Lowpower mode; STBCL = 1; see
completely switched off (Off mode; STBCL = 0) - see
running in Timeout mode or Off mode, depending on the state of the WDOFF pin and the
setting of the watchdog mode control bit (WMC) in the WD_and_Status register
The SBC will exit Standby mode if:
Normal mode is selected from Standby mode by setting bits MC in the Mode_Control
register
In Normal mode, the LIN physical layer (LIN) will be enabled (Active mode; STBCL = 0;
see
detection active.
The SBC will exit Normal mode if:
w(rst)
•
•
•
•
•
•
•
•
•
•
•
From Off mode if V
From Sleep mode on the occurrence of a LIN or local wake-up event
From Overtemp mode if the chip temperature drops below the overtemperature
protection release threshold, T
From Normal mode if bit MC is set to 00 or a system reset is performed (see
Section
Normal mode is selected by setting bits MC to 10 or 11
Sleep mode is selected by setting bits MC to 01
The chip temperature rises above the OverTemperature Protection (OTP) activation
threshold, T
Standby mode is selected by setting bits MC to 00
Sleep mode is selected by setting bits MC to 01
A system reset is generated (see
The chip temperature rises above the OTP activation threshold, T
SBC to switch to Overtemp mode
Table
, long or short; see
(Table
6) or in a low-power state (Lowpower mode; STBCL = 1) with bus wake-up
6.5)
5) to 10 or 11.
All information provided in this document is subject to legal disclaimers.
th(act)otp
Rev. 2 — 31 January 2011
BAT
, causing the SBC to enter Overtemp mode
Section 6.5.1
rises above the power-on detection threshold (V
th(det)poff
th(rel)otp
Section
and
). In Off mode, the voltage regulator is disabled
Table
Table
6.1.3; the SBC will enter Standby mode)
6) with bus wake-up detection enabled or
11).
Section
LIN core system basis chip
6.7.1. The watchdog can be
UJA1079A
th(act)otp
© NXP B.V. 2011. All rights reserved.
th(det)pon
, causing the
th(det)pon
(Table
)
9 of 46
),
4).