UJA1061TW/5V0/C/T/ NXP Semiconductors, UJA1061TW/5V0/C/T/ Datasheet - Page 43

• Manufacturer Part Number: UJA1061TW/5V0/C/T/
• Description: IC CAN/LIN FAIL-SAFE HS 32HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1061TW/5V0/C/T/

• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Applications: Automotive Networking
• Interface: CAN, LIN
• Voltage - Supply: 5.5 V ~ 27 V
• Mounting Type: Surface Mount
• Product: Controller Area Network (CAN)
• Number Of Transceivers: 2
• Supply Voltage (max): 27 V, 52 V
• Supply Voltage (min): 5.5 V
• Supply Current (max): 10 mA, 25 mA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935288866512

NXP Semiconductors
Table 22.
Table 23.
Table 24.
UJA1061_6
Product data sheet
Symbol
ISDM
ERREM
WDPRE
V1RTHC
Symbol
DIC
GP0[10:7]
GP0[6:0]
Symbol
GP1[11:0]
Special Mode register: status at reset
General Purpose register 0 and General Purpose Feedback register 0: status at reset
General Purpose register 1 and General Purpose Feedback register 1: status at reset
6.14.1 Software Development mode
6.14 Test modes
Name
Initialize Software Development Mode
Error pin emulation mode
Watchdog Prescale Factor
V1 Reset Threshold Control
Name
Device Identification Control
general purpose bits 10 to 7 (version)
general purpose bits 6 to 0 (SBC type)
Name
general purpose bits 11 to 0
The Software Development mode is intended to support software developers in writing
and pretesting application software without having to work around watchdog triggering
and without unwanted jumps to Fail-safe mode.
In Software Development mode the following events do not force of a system reset:
However, in case of a watchdog trigger failure the reset source information is still provided
in the System Status register as if there was a real reset event.
The exclusion of watchdog related resets allows simplified software testing, because
possible problems in the watchdog triggering can be indicated by interrupts instead of
resets. The SDM bit does not affect the watchdog behavior in Standby and Sleep mode.
This allows the cyclic wake-up behavior to be evaluated during Standby and Sleep mode
of the SBC.
All transitions to Fail-safe mode are disabled. This allows working with an external
emulator that clamps the reset line LOW in debugging mode. A V1 undervoltage of more
than t
SBC). Transitions from Start-up mode to Restart mode are still possible.
•
•
•
•
Watchdog overflow in Normal mode
Watchdog window miss
Interrupt time-out
Elapsed start-up time
V1(CLT)
is the only exception that results in entering Fail-safe mode (to protect the
All information provided in this document is subject to legal disclaimers.
Rev. 06 — 9 March 2010
00 (factor 1)
0000 0000 0000
Power-on
0 (no)
0 (EN function)
00 (90 %)
Power-on
0 (Device ID)
Mask version
000 0001
(UJA1061)
Power-on
Fault-tolerant CAN/LIN fail-safe system basis chip
Start-up
no change
no change
no change
no change
Start-up
no change
no change
no change
Start-up
no change
UJA1061
© NXP B.V. 2010. All rights reserved.
Restart
no change
no change
no change
00 (90 %)
Restart
no change
no change
no change
Restart
no change
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