UJA1061TW/5V0/C/T, NXP Semiconductors, UJA1061TW/5V0/C/T, Datasheet - Page 29

• Manufacturer Part Number: UJA1061TW/5V0/C/T,
• Description: IC CAN/LIN FAIL-SAFE HS 32HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1061TW/5V0/C/T,

• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Applications: Automotive Networking
• Interface: CAN, LIN
• Voltage - Supply: 5.5 V ~ 27 V
• Mounting Type: Surface Mount
• Product: Controller Area Network (CAN)
• Number Of Transceivers: 2
• Supply Voltage (max): 27 V or 52 V
• Supply Voltage (min): 5.5 V
• Supply Current (max): 10 mA or 25 mA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935288866518

NXP Semiconductors
Table 4.
UJA1061_6
Product data sheet
Register
address bits
(A1, A0)
00
01
10
11
Register overview
6.13.2 Register overview
6.13.3 Mode register
all modes
Normal mode;
Normal mode;
Operating
mode
Standby mode;
Flash mode
Start-up mode;
Restart mode
Standby mode
Start-up mode;
Restart mode;
Flash mode
Normal mode;
Standby mode
Start-up mode;
Restart mode;
Flash mode
Each register carries 12 data bits; the other 4 bits are used for register selection and
read/write definition.
The SPI interface gives access to all SBC registers; see
A0) of the message header define the register address, the third bit is the read register
select bit (RRS) to select one out of two possible feedback registers; the fourth bit (RO)
allows ‘read only’ access to one of the feedback registers. Which of the SBC registers can
be accessed also depends on the SBC operating mode.
In the Mode register the watchdog is defined and re-triggered, and the SBC operating
mode is selected. The Mode register also contains the global enable output bit (EN) and
the Software Development Mode (SDM) control bit. During system operation cyclic
access to the Mode register is required to serve the watchdog. This register can be written
to in all modes.
At system start-up the Mode register must be written to within t
RSTN (HIGH-level on pin RSTN). Any write access is checked for proper watchdog and
system mode coding. If an illegal code is detected, access is ignored by the SBC and a
system reset is forced in accordance with the state diagram of the system controller; see
Figure
3.
Write access (RO = 0)
Mode register
Interrupt Enable register
Special Mode register
System Configuration
register
General Purpose register 0
Physical Layer Control
register
General Purpose register 1
All information provided in this document is subject to legal disclaimers.
Rev. 06 — 9 March 2010
Read access (RO = 0 or RO = 1)
Read Register Select
(RRS) bit = 0
System Status register
Interrupt Enable Feedback
register
Interrupt Enable Feedback
register
System Configuration
Feedback register
System Configuration
Feedback register
Physical Layer Control
Feedback register
Physical Layer Control
Feedback register
Fault-tolerant CAN/LIN fail-safe system basis chip
Table
4. The first two bits (A1 and
WD(init)
Read Register Select
(RRS) bit = 1
System Diagnosis register
Interrupt register
Special Mode Feedback
register
General Purpose Feedback
register 0
General Purpose Feedback
register 0
General Purpose Feedback
register 1
General Purpose Feedback
register 1
from releasing
UJA1061
© NXP B.V. 2010. All rights reserved.
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