UJA1061TW/5V0/C/T, NXP Semiconductors, UJA1061TW/5V0/C/T, Datasheet - Page 5

• Manufacturer Part Number: UJA1061TW/5V0/C/T,
• Description: IC CAN/LIN FAIL-SAFE HS 32HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1061TW/5V0/C/T,

• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Applications: Automotive Networking
• Interface: CAN, LIN
• Voltage - Supply: 5.5 V ~ 27 V
• Mounting Type: Surface Mount
• Product: Controller Area Network (CAN)
• Number Of Transceivers: 2
• Supply Voltage (max): 27 V or 52 V
• Supply Voltage (min): 5.5 V
• Supply Current (max): 10 mA or 25 mA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935288866518

NXP Semiconductors
5. Pinning information
UJA1061_6
Product data sheet
5.1 Pinning
5.2 Pin description
Table 2.
Symbol
n.c.
n.c.
TXDL
V1
RXDL
RSTN
INTN
EN
SDI
SDO
SCK
SCS
TXDC
RXDC
n.c.
TEST
Fig 2.
Pin configuration
Pin description
1
2
4
5
6
7
8
10
12
13
14
15
16
Pin
3
9
11
All information provided in this document is subject to legal disclaimers.
Description
not connected
not connected
LIN transmit data input (LOW for dominant, HIGH for recessive)
voltage regulator output for the microcontroller (3.3 V or 5 V depending on
the SBC version)
LIN receive data output (LOW when dominant, HIGH when recessive)
reset output to microcontroller (active LOW; will detect clamping situations)
interrupt output to microcontroller (active LOW; open-drain, wire-AND this pin
to other ECU interrupt outputs)
enable output (active HIGH; push-pull, LOW with every reset / watchdog
overflow)
SPI data input
SPI data output (floating when pin SCS is HIGH)
SPI clock input
SPI chip select input (active LOW)
CAN transmit data input (LOW for dominant; HIGH for recessive)
CAN receive data output (LOW when dominant; HIGH when recessive)
not connected
test pin (should be connected to ground in application)
RXDC
RSTN
TXDC
RXDL
TXDL
TEST
INTN
SDO
SCK
SCS
Rev. 06 — 9 March 2010
SDI
n.c.
n.c.
n.c.
EN
V1
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Fault-tolerant CAN/LIN fail-safe system basis chip
UJA1061
001aad604
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
BAT42
RESERVED
V3
SYSINH
n.c.
BAT14
RTLIN
LIN
RTH
GND
CANL
CANH
V2
RTL
WAKE
INH/LIMP
UJA1061
© NXP B.V. 2010. All rights reserved.
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