KIT33730EKEVBE Freescale Semiconductor, KIT33730EKEVBE Datasheet - Page 17

• Manufacturer Part Number: KIT33730EKEVBE
• Description: Power Management Modules & Development Tools SWITCH MODE PWR SUP
• Manufacturer: Freescale Semiconductor
• Type: Linear Regulators - Standardr

Specifications of KIT33730EKEVBE

• Product: Power Management Modules
• Silicon Manufacturer: Freescale
• Silicon Core Number: MC33730
• Kit Application Type: Power Management
• Application Sub Type: SMPS
• Kit Contents: Board, CD
• Rohs Compliant: Yes
• For Use With/related Products: MC33730
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PROGRAMMING LINEAR REGULATOR OUTPUT
VOLTAGE
can be externally programmed by placing logic levels on the
programming pins P1, P2, and P3 (see
extends the application flexibility of the IC without having to
use an external resistor divider, thus improving the regulator
accuracy over the whole temperature range, and reducing
the component count.
selected by tying the pin to ground (logic level "0") or to
protected battery voltage (logic level "1"). Programming pins
must never be left floating, they must be tied to either ground
or protected battery voltage.
500 μs delay after the power is applied to the IC.
Table 6. Programming VDD3, VDDL, VKAM Output
LOW BATTERY OPERATION
minimum value, the 33730 switching regulator will enter a
100% duty cycle mode of operation and its output voltage
V
voltage continues to fall, the V
threshold level, and the RSTH signal will be pulled low, but
the other linear regulators will continue to operate, and their
monitoring signals stay high as long as the VDDH provides
sufficient headroom for the regulators to stay in their
regulation limits (see
voltage continues to fall, the linear regulators would not have
sufficient headroom to stay in regulation, and their resets
would be asserted (RSTL, RST3, or both would be pulled
low). At that moment the power down sequence would be
engaged.
V
Analog Integrated Circuit Device Data
Freescale Semiconductor
DDH
KAM_DO)
The Programming Pins can be tied high, to protected battery
voltage, or low, to ground.
High
High
High
High
The output voltage of the VDD3, VDDL and VKAM outputs
The logic level of the programming pin (Px) can be
The programming information is read and latched with the
Low
Low
Low
Low
When the battery voltage falls below the specified
The V
P1
will follow the decreasing battery voltage. If the battery
KAM
and V
High
High
High
High
Low
Low
Low
Low
P2
Voltage
standby regulator will operate down to (V
KAM-DO
High
High
High
High
Low
Low
Low
Low
P3
Figure 6
at the KA_VBAT pin.
3.3 V Standby
2.6 V Standby
2.6 V Standby
V
3.3 V
3.3 V
3.3 V
3.3 V
2.0 V
DDH
and
DD3
voltage reaches its reset
Figure
Table
3.15 V
V
7). If the battery
2.6 V
3.3 V
1.5 V
3.3 V
3.3 V
3.3 V
3.3 V
DDL
6). This
V
2.6 V
3.3 V
1.0 V
1.0 V
1.0 V
5.0 V
1.0 V
1.5 V
KAM
KAM and
POWER SEQUENCING (VDDH, VDD3, VDDL)
internal pull-down FETs. During the power up sequence,
V
outputs will be pulled down by the internal pull-down power
FETs, and V
typ.).
following conditions have to be met:
standby regulator.
SENSOR SUPPLIES (VREF1, VREF2)
integrated into the IC. They are internally connected to V
through power MOSFETs which protect against short to
battery and short to ground conditions.
like shorts to either ground or battery, will not disrupt the
operation of the main regulator V
any Reset signal.
transient voltage events with slew rates faster than
2.0 V/μs, otherwise damage to the part may occur. A
practical and inexpensive solution consists of using a series
RC network connected from the VREF output to ground (see
Figures 8
such as a single electrolytic capacitor with its capacitance
value C > 10 μF, may be also used.
PROTECTION FET DRIVE (PFD)
N-channel protection MOSFET (instead of a standard
reverse protection diode) to protect against a reverse battery
voltage condition. This approach improves the operating
capabilities at very low battery voltages.
Protection FET gate during nominal and low battery
conditions. The charge pump will be enabled at the startup
voltage. When the battery voltage gets sufficiently high, the
Protection FET is turned off and the integrated circuit power
input (V
Protection FET.
already using a protection diode, relay or when no reverse
battery protection is required.
CONTROL INPUT (VIGN)
regulation circuits will function and draw current from V
when V
The VIGN pin has a
DD3
V
During the power down sequence the V
In order to engage the power down sequence, the
(VIGN . REGON) + UVLO = Power Down
The VDD3 output is not power sequenced when used as a
There are two sensor supplies, VREF1 and VREF2,
Severe fault conditions on the VREF1 and VREF2 outputs,
IMPORTANT NOTE:
The VREF outputs MUST be externally protected against
The Protection FET Drive circuit allows using an optional
An internal charge pump is used to enhance the
Use of the Protection FET is not necessary in systems
The VIGN pin is used as a control input to the IC. The
DDH
and V
IGN
BAT
, V
and
DD3
is high (active) or when the REGON pin is high.
DDL
DDH
pins) are supplied through the body diode of the
, and V
9
will follow V
for typical component values). Other means,
will be shut off with a defined delay (~100 μs
V
DDL
IHN-IH
are power sequenced by means of
FUNCTIONAL DEVICE OPERATION
power-up threshold
DDH
.
DDH
OPERATION DESCRIPTION
, or cause assertion of
DD3
V
and V
IGN-IL
DDL
typical
BAT
33730
DDH
17