ATTINY461V-10PU Atmel, ATTINY461V-10PU Datasheet - Page 87
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ATTINY461V-10PU
Manufacturer Part Number
ATTINY461V-10PU
Description
Microcontrollers (MCU) 4kB Flash 0.256kB EEPROM 16 I/O Pins
Manufacturer
Atmel
Specifications of ATTINY461V-10PU
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
2-Wire/SPI/USI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Program Memory Type
Flash
Program Memory Size
4 KB
Package / Case
PDIP-20
Package
20PDIP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
10 MHz
Ram Size
256 Byte
Operating Temperature
-40 to 85 °C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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11.10.8
2588E–AVR–08/10
TIFR – Timer/Counter0 Interrupt Flag Register
if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the
Timer/Counter 0 Interrupt Flag Register – TIFR0.
• Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter
Interrupt Flag Register – TIFR0.
• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Inter-
rupt Flag Register – TIFR0.
• Bit 0 – TICIE0: Timer/Counter0, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector
• Bit 4 – OCF0A: Output Compare Flag 0 A
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data
in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the cor-
responding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable),
and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.
The OCF0A is also set in 16-bit mode when a Compare Match occurs between the Timer/Coun-
ter and 16-bit data in OCR0B/A. The OCF0A is not set in Input Capture mode when the Output
Compare Register OCR0A is used as an Input Capture Register.
• Bit 3 – OCF0B: Output Compare Flag 0 B
The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in
OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the cor-
responding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable),
and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.
The OCF0B is not set in 16-bit Output Compare mode when the Output Compare Register
OCR0B is used as the high byte of the 16-bit Output Compare Register or in 16-bit Input Cap-
ture mode when the Output Compare Register OCR0B is used as the high byte of the Input
Capture Register.
Bit
0x38 (0x58)
Read/Write
Initial Value
(See “Interrupts” on page
OCF1D
R/W
7
0
OCF1A
R/W
6
0
50.) is executed when the ICF0 flag, located in TIFR, is set.
OCF1B
R/W
5
0
OCF0A
R/W
4
0
OCF0B
R/W
3
0
TOV1
R/W
2
0
TOV0
R/W
1
0
ICF0
R
0
0
TIFR
87
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