A2F200M3F-1FGG256 Actel, A2F200M3F-1FGG256 Datasheet - Page 22
![FPGA - Field Programmable Gate Array 200K System Gates SmartFusion](/photos/16/14/161496/lpsilverchip_sml.jpg)
A2F200M3F-1FGG256
Manufacturer Part Number
A2F200M3F-1FGG256
Description
FPGA - Field Programmable Gate Array 200K System Gates SmartFusion
Manufacturer
Actel
Datasheet
1.A2F500M3G-FGG256.pdf
(192 pages)
Specifications of A2F200M3F-1FGG256
Processor Series
A2F200
Core
ARM Cortex M3
Number Of Logic Blocks
8
Maximum Operating Frequency
120 MHz
Number Of Programmable I/os
117
Data Ram Size
4608 bit
Delay Time
200 ns
Supply Voltage (max)
3.6 V
Supply Current
3 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
200000
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A2F200M3F-1FGG256
Manufacturer:
ACT
Quantity:
36
Company:
Part Number:
A2F200M3F-1FGG256
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A2F200M3F-1FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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SmartFusion DC and Switching Characteristics
Calculating Power Dissipation
Table 2-8 • Quiescent Supply Current Characteristics
Table 2-9 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
2- 10
Modes and Power
Supplies
Time Keeping mode
Standby mode
Parameter
IDC1
IDC2
Note:
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
3.3 V PCI
3.3 V PCI-X
Differential
LVDS
LVPECL
*On means proper voltage is applied. Refer to
Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
Quiescent Supply Current
Power per I/O Pin
Modes
Time Keeping mode
Standby mode
On*
0 V
3.3 V
0 V
Power Supplies Configuration
VCCFPGAIOBx (V)
1.5 V Domain
1.5 V
0 V
3 mA
N/A
3.3
2.5
1.8
1.5
3.3
3.3
2.5
3.3
Table 2-3 on page 2-3
3.3 V
N/A
R e visio n 6
A2F200
3.3 V Domain
3.3 V
0 V
10 µA
1 mA
Static Power
PDC7 (mW)
N/A
0 V
2.26
5.72
for recommended operating conditions.
–
–
–
–
–
–
1.5 V Domain
N/A
0 V
TBD
N/A
Reset
Off
Dynamic Power PAC9
Enable
Enable
A2F500
(µW/MHz)
3.3 V Domain
17.55
19.21
19.21
5.97
2.88
2.33
0.82
1.16
10 µA
1 mA
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