A2F200M3F-1FGG256 Actel, A2F200M3F-1FGG256 Datasheet - Page 80
![FPGA - Field Programmable Gate Array 200K System Gates SmartFusion](/photos/16/14/161496/lpsilverchip_sml.jpg)
A2F200M3F-1FGG256
Manufacturer Part Number
A2F200M3F-1FGG256
Description
FPGA - Field Programmable Gate Array 200K System Gates SmartFusion
Manufacturer
Actel
Datasheet
1.A2F500M3G-FGG256.pdf
(192 pages)
Specifications of A2F200M3F-1FGG256
Processor Series
A2F200
Core
ARM Cortex M3
Number Of Logic Blocks
8
Maximum Operating Frequency
120 MHz
Number Of Programmable I/os
117
Data Ram Size
4608 bit
Delay Time
200 ns
Supply Voltage (max)
3.6 V
Supply Current
3 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
200000
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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A2F200M3F-1FGG256
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Company:
Part Number:
A2F200M3F-1FGG256
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Part Number:
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Quantity:
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SmartFusion DC and Switching Characteristics
Table 2-85 • RAM4K9
2- 68
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
F
Note:
AS
AH
ENS
ENH
BKS
BKH
DS
DH
CKQ1
CKQ2
C2CWWH
C2CRWH
C2CWRH
RSTBQ
REMRSTB
RECRSTB
MPWRSTB
CYC
MAX
For the derating values at specific junction temperature and voltage supply levels, refer to
page 2-9
Worst Commercial-Case Conditions: T
Timing Characteristics
Address setup time
Address hold time
REN_B, WEN_B setup time
REN_B, WEN_B hold time
BLK_B setup time
BLK_B hold time
Input data (DI) setup time
Input data (DI) hold time
Clock High to new data valid on DO (output retained, WMODE = 0)
Clock High to new data valid on DO (flow-through, WMODE = 1)
Clock High to new data valid on DO (pipelined)
Address collision clk-to-clk delay for reliable write after write on same
address—applicable to rising edge
Address collision clk-to-clk delay for reliable read access after write on same
address—applicable to opening edge
Address collision clk-to-clk delay for reliable write access after read on same
address— applicable to opening edge
RESET_B Low to data out Low on DO (flow-through)
RESET_B Low to Data Out Low on DO (pipelined)
RESET_B removal
RESET_B recovery
RESET_B minimum pulse width
Clock cycle time
Maximum clock frequency
for derating values.
Description
J
= 85°C, Worst-Case VCC = 1.425 V
R e visio n 6
0.25
0.00
0.15
0.10
0.24
0.02
0.19
0.00
1.81
2.39
0.91
0.30
0.45
0.49
0.94
0.94
0.29
1.52
0.22
3.28
305
–1
0.30
0.00
0.17
0.12
0.28
0.02
0.22
0.00
2.18
2.87
1.09
0.35
0.52
0.57
1.12
1.12
0.35
1.83
0.22
3.28
Table 2-7 on
Std.
305
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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