A2F200M3F-1FGG256 Actel, A2F200M3F-1FGG256 Datasheet - Page 65
![FPGA - Field Programmable Gate Array 200K System Gates SmartFusion](/photos/16/14/161496/lpsilverchip_sml.jpg)
A2F200M3F-1FGG256
Manufacturer Part Number
A2F200M3F-1FGG256
Description
FPGA - Field Programmable Gate Array 200K System Gates SmartFusion
Manufacturer
Actel
Datasheet
1.A2F500M3G-FGG256.pdf
(192 pages)
Specifications of A2F200M3F-1FGG256
Processor Series
A2F200
Core
ARM Cortex M3
Number Of Logic Blocks
8
Maximum Operating Frequency
120 MHz
Number Of Programmable I/os
117
Data Ram Size
4608 bit
Delay Time
200 ns
Supply Voltage (max)
3.6 V
Supply Current
3 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
200000
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A2F200M3F-1FGG256
Manufacturer:
ACT
Quantity:
36
Company:
Part Number:
A2F200M3F-1FGG256
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A2F200M3F-1FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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Output DDR Module
Figure 2-21 • Output DDR Timing Model
Table 2-75 • Parameter Definitions
Parameter Name
t
t
t
t
t
t
t
t
DDROCLKQ
DDROCLR2Q
DDROREMCLR
DDRORECCLR
DDROSUD1
DDROSUD2
DDROHD1
DDROHD2
Data_R
(from core)
Data_F
(from core)
CLK
CLR
Clock-to-Out
Asynchronous Clear-to-Out
Clear Removal
Clear Recovery
Data Setup Data_F
Data Setup Data_R
Data Hold Data_F
Data Hold Data_R
INBUF
CLKBUF
Parameter Definition
D
C
A
B
C
B
X
X
X
X
X
X
R e v i s i o n 6
FF1
FF2
Output DDR
DDR_OUT
SmartFusion Intelligent Mixed Signal FPGAs
0
1
Measuring Nodes (from, to)
E
X
Out
OUTBUF
C, E
B, E
C, B
C, B
A, B
D, B
A, B
D, B
2- 53
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