A2F200M3F-1FGG256 Actel, A2F200M3F-1FGG256 Datasheet - Page 36
A2F200M3F-1FGG256
Manufacturer Part Number
A2F200M3F-1FGG256
Description
FPGA - Field Programmable Gate Array 200K System Gates SmartFusion
Manufacturer
Actel
Datasheet
1.A2F500M3G-FGG256.pdf
(192 pages)
Specifications of A2F200M3F-1FGG256
Processor Series
A2F200
Core
ARM Cortex M3
Number Of Logic Blocks
8
Maximum Operating Frequency
120 MHz
Number Of Programmable I/os
117
Data Ram Size
4608 bit
Delay Time
200 ns
Supply Voltage (max)
3.6 V
Supply Current
3 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
200000
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A2F200M3F-1FGG256
Manufacturer:
ACT
Quantity:
36
Company:
Part Number:
A2F200M3F-1FGG256
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A2F200M3F-1FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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SmartFusion DC and Switching Characteristics
2- 24
Table 2-20 • Summary of Maximum and Minimum DC Input Levels
Summary of I/O Timing Characteristics – Default I/O Software
Settings
Table 2-21 • Summary of AC Measuring Points Applicable to All I/O Bank Types
Table 2-22 • I/O AC Parameter Definitions
DC I/O Standards
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
3.3 V PCI-X
Standard
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
3.3 V PCI-X
LVDS
LVPECL
Parameter
t
t
t
t
t
t
t
t
t
t
t
DP
PY
DOUT
EOUT
DIN
HZ
ZH
LZ
ZL
ZHS
ZLS
Applicable to Commercial Conditions in all I/O Bank Types
Data to pad delay through the output buffer
Pad to data delay through the input buffer
Data to output buffer delay through the I/O interface
Enable to output buffer tristate control delay through the I/O interface
Input buffer to data delay through the I/O interface
Enable to pad delay through the output buffer—High to Z
Enable to pad delay through the output buffer—Z to High
Enable to pad delay through the output buffer—Low to Z
Enable to pad delay through the output buffer—Z to Low
Enable to pad delay through the output buffer with delayed enable—Z to High
Enable to pad delay through the output buffer with delayed enable—Z to Low
R e visio n 6
Parameter Definition
Measuring Trip Point (V
0.285 * VCCxxxxIOBx (RR)
0.285 * VCCxxxxIOBx (RR)
0.615 * VCCxxxxIOBx (FF)
0.615 * VCCxxxxIOBx (FF)
µA
15
15
15
15
15
15
I
IL
Cross point
Cross point
0.90 V
0.75 V
1.4 V
1.2 V
Commercial
trip
)
µA
I
15
15
15
15
15
15
IH
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