APA150-TQG100 Actel, APA150-TQG100 Datasheet - Page 11

• Manufacturer Part Number: APA150-TQG100
• Description: FPGA - Field Programmable Gate Array 150K System Gates
• Manufacturer: Actel

Specifications of APA150-TQG100

• Processor Series: APA150
• Core: IP Core
• Maximum Operating Frequency: 150 MHz
• Number Of Programmable I/os: 242
• Data Ram Size: 36864
• Supply Voltage (max): 2.7 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: APA-Eval-Kit, APA-Eval-BRD1, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.3 V
• Number Of Gates: 150 K
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

General Description
Routing Resources
The routing structure of ProASIC
to provide high performance through a flexible four-
level hierarchy of routing resources: ultra-fast local
resources, efficient long-line resources, high-speed, very
long-line resources, and high performance global
networks.
The ultra-fast local resources are dedicated lines that
allow the output of each tile to connect directly to every
input of the eight surrounding tiles
The efficient long-line resources provide routing for
longer distances and higher fanout connections. These
resources vary in length (spanning 1, 2, or 4 tiles), run
both vertically and horizontally, and cover the entire
ProASIC
drive signals onto the efficient long-line resources, which
Figure 2-1 • Ultra-Fast Local Resources
PLUS
device
(Figure 2-2 on page
L
L
L
PLUS
Inputs
(Figure
devices is designed
2-2). Each tile can
2-1).
L
L
L
v5.9
can in turn access every input of every tile. Active buffers
are inserted automatically by routing software to limit
the loading effects due to distance and fanout.
The high-speed, very long-line resources, which span the
entire device with minimal delay, are used to route very
long or very high fanout nets.
The high-performance global networks are low-skew,
high fanout nets that are accessible from external pins or
from internal logic
are typically used to distribute clocks, resets, and other
high fanout nets requiring a minimum skew. The global
networks are implemented as clock trees, and signals can
be introduced at any junction. These can be employed
hierarchically with signals accessing every input on all
tiles.
L
L
L
(Figure 2-4 on page
Ultra-Fast
Local Lines
(connects a tile to the
adjacent tile, I/O buffer,
or memory block)
ProASIC
(Figure 2-3 on page
PLUS
Flash Family FPGAs
2-4). These nets
2-3).
2-1