AFS250-PQG208 Actel, AFS250-PQG208 Datasheet - Page 103
AFS250-PQG208
Manufacturer Part Number
AFS250-PQG208
Description
FPGA - Field Programmable Gate Array 250K System Gates
Manufacturer
Actel
Datasheet
1.AFS600-PQG208.pdf
(330 pages)
Specifications of AFS250-PQG208
Processor Series
AFS250
Core
IP Core
Maximum Operating Frequency
1098.9 MHz
Number Of Programmable I/os
93
Data Ram Size
36864
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
250 K
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 2-68 • Analog Quad Prescaler Input Configuration
Off-Chip
On-Chip
Pads
The Analog Quad offers a wide variety of prescaling options to enable the ADC to resolve the input
signals.
conversion. The ADC internal reference voltage and the prescaler factors were selected to make both
prescaling and postscaling of the signals easy binary calculations (refer to
details). When an analog input pad is configured with a prescaler, there will be a 1 MΩ resistor to ground.
This occurs even when the device is in power-down mode. In low power standby or sleep mode (V
OFF, V
ground through a 1 MΩ resistor. The gate driver output is floating (or tristated), and there is no extra
current on V
These scaling factors hold true whether the particular pad is configured to accept a positive or negative
voltage. Note that whereas the AV and AC pads support the same prescaling factors, the AT pad
supports a reduced set of prescaling factors and supports positive voltages only.
Typical scaling factors are given in
minimum and maximum) is in
AV
Digital
Prescaler
Input
Monitor Block
CC33A
Figure 2-68
Voltage
(DAVOUTx)
CC33A
To FPGA
is ON, V
To Analog MUX
.
shows the path through the Analog Quad for a signal that is to be prescaled prior to
CCI
Monitor / Instr
is ON) or when the resource is not used, analog inputs are pulled down to
AC
Amplifier
Digital
Prescaler
Current
Input
Table 2-46 on page
Monitor Block
Table 2-54 on page
(DACOUTx)
Current
To FPGA
Analog Quad
To Analog MUX
R e v i s i o n 1
2-119.
Gate Driver
From FPGA
MOSFET
(GDONx)
2-132, and the gain error (which contributes to the
Power
AG
Driver
Gate
Actel Fusion Family of Mixed Signal FPGAs
AT
Table 2-54 on page 2-132
Temperature
Digital
Input
Prescaler
Monitor
Monitor Block
Temperature
(DATOUTx)
To FPGA
To Analog MUX
CC
2- 87
for
is
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