AFS250-PQG208 Actel, AFS250-PQG208 Datasheet - Page 54
AFS250-PQG208
Manufacturer Part Number
AFS250-PQG208
Description
FPGA - Field Programmable Gate Array 250K System Gates
Manufacturer
Actel
Datasheet
1.AFS600-PQG208.pdf
(330 pages)
Specifications of AFS250-PQG208
Processor Series
AFS250
Core
IP Core
Maximum Operating Frequency
1098.9 MHz
Number Of Programmable I/os
93
Data Ram Size
36864
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
250 K
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
Quantity
Price
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Part Number:
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MPS
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Company:
Part Number:
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Microsemi SoC
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Part Number:
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Device Architecture
2- 38
Table 2-17 • VRPSM Signal Descriptions
Signal Name
VRPU
VRINITSTATE
RTCPSMMATCH
PUB
TRST*
FPGAGOOD
PUCORE
VREN*
Note:
*Signals are hardwired internally and do not exist in the macro core.
Width Dir.
1
1
1
1
1
1
1
1
Out Indicator that the FPGA is powered and functional
Out Power-Up Core
Out Voltage Regulator Enable
In Voltage Regulator Power-Up
In Voltage Regulator Initial State
In RTC Power System Management Match
In External pin, built-in weak pull-up
In External pin, JTAG Test Reset
0 – Voltage regulator disabled. PUB must be floated or pulled up, and
the TRST pin must be grounded to disable the voltage regulator.
1 – Voltage regulator enabled
Defines the voltage Regulator status upon power-up of the 3.3 V. The
signal is configured by Actel Libero
(IDE) when the VRPSM macro is generated.
Tie off to 1 – Voltage regulator enables when 3.3 V is powered.
Tie off to 0 – Voltage regulator disables when 3.3 V is powered.
Connect from RTCPSMATCH signal from RTC in AB
0 transition to 1 turns on the voltage regulator
Power-Up Bar
0 – Enables voltage regulator at all times
1 – Enables voltage regulator at all times
No need to connect if it is not used.
1 – Indicates that the FPGA is powered up and functional.
0 – Not possible to read by FPGA since it has already powered off.
Inverted signal of PUB. No need to connect if it is not used.
Connected to 1.5 V voltage regulator in Fusion device internally.
0 – Voltage regulator disables
1 – Voltage regulator enables
R e visio n 1
Function
®
Integrated Design Environment
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