AFS250-PQG208 Actel, AFS250-PQG208 Datasheet - Page 77

• Manufacturer Part Number: AFS250-PQG208
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of AFS250-PQG208

• Processor Series: AFS250
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 93
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The following signals are used to configure the RAM4K9 memory element:
WIDTHA and WIDTHB
These signals enable the RAM to be configured in one of four allowable aspect ratios
Table 2-27 • Allowable Aspect Ratio Settings for WIDTHA[1:0]
BLKA and BLKB
These signals are active low and will enable the respective ports when asserted. When a BLKx signal is
deasserted, the corresponding port’s outputs hold the previous value.
WENA and WENB
These signals switch the RAM between read and write mode for the respective ports. A Low on these
signals indicates a write operation, and a High indicates a read.
CLKA and CLKB
These are the clock signals for the synchronous read and write operations. These can be driven
independently or with the same driver.
PIPEA and PIPEB
These signals are used to specify pipelined read on the output. A Low on PIPEA or PIPEB indicates a
nonpipelined read, and the data appears on the corresponding output in the same clock cycle. A High
indicates a pipelined, read and data appears on the corresponding output in the next clock cycle.
WMODEA and WMODEB
These signals are used to configure the behavior of the output when the RAM is in write mode. A Low on
these signals makes the output retain data from the previous read. A High indicates pass-through
behavior, wherein the data being written will appear immediately on the output. This signal is overridden
when the RAM is being read.
RESET
This active low signal resets the output to zero, disables reads and writes from the SRAM block, and
clears the data hold registers when asserted. It does not reset the contents of the memory.
ADDRA and ADDRB
These are used as read or write addresses, and they are 12 bits wide. When a depth of less than 4 k is
specified, the unused high-order bits must be grounded
Table 2-28 • Address Pins Unused/Used for Various Supported Bus Widths
WIDTHA1, WIDTHA0
00
01
10
11
Note:
D×W
4k×1
2k×2
1k×4
512×9
Note:
The aspect ratio settings are constant and cannot be changed on the fly.
The "x" in ADDRx implies A or B.
Unused
[11:10]
None
[11:9]
[11]
R e v i s i o n 1
WIDTHB1, WIDTHB0
(Table
ADDRx
00
01
10
2-28).
11
Actel Fusion Family of Mixed Signal FPGAs
Used
[10:0]
[11:0]
[9:0]
[8:0]
(Table
512×9
D×W
2-27).
4k×1
2k×2
1k×4
2- 61