AFS250-PQG208 Actel, AFS250-PQG208 Datasheet - Page 168
AFS250-PQG208
Manufacturer Part Number
AFS250-PQG208
Description
FPGA - Field Programmable Gate Array 250K System Gates
Manufacturer
Actel
Datasheet
1.AFS600-PQG208.pdf
(330 pages)
Specifications of AFS250-PQG208
Processor Series
AFS250
Core
IP Core
Maximum Operating Frequency
1098.9 MHz
Number Of Programmable I/os
93
Data Ram Size
36864
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
250 K
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Device Architecture
Figure 2-108 • Example of Implementation of Skew Circuits in Bidirectional Transmission Systems Using
Figure 2-109 • Timing Diagram (bypasses skew circuit)
2- 15 2
Skew or
Bypass
Skew
Transmitter 1: OFF
Transmitter 2: ON
ENABLE(t1)
Transmitter 1: Fusion I/O
At the system level, the skew circuit can be used in applications where transmission activities on
bidirectional data lines need to be coordinated. This circuit, when selected, provides a timing margin that
can prevent bus contention and subsequent data loss or transmitter overstress due to transmitter-to-
transmitter current shorts.
bidirectional communication system.
110 on page 2-153
Fusion Devices
ENABLE (t2)
ENABLE (r1)
ENABLE (t1)
EN(r1)
EN (b1)
EN (b2)
Delay (t1)
Routing
shows how it can be avoided with the skew circuit.
EN(b1)
Contention
Figure 2-108
Bus
Transmitter 1: ON
Bidirectional Data Bus
Transmitter
ENABLE/
DISABLE
Figure 2-109
presents an example of the skew circuit implementation in a
Transmitter 2: OFF
R e visio n 1
shows how bus contention is created, and
EN(b2)
Transmitter 2: Generic I/O
Transmitter 1: OFF
Delay (t2)
Routing
ENABLE(t2)
Figure 2-
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