A54SX32A-PQ208 Actel, A54SX32A-PQ208 Datasheet - Page 24

• Manufacturer Part Number: A54SX32A-PQ208
• Description: FPGA - Field Programmable Gate Array 32K System Gates
• Manufacturer: Actel

Specifications of A54SX32A-PQ208

• Processor Series: A54SX32
• Core: IP Core
• Number Of Macrocells: 1800
• Maximum Operating Frequency: 238 MHz
• Number Of Programmable I/os: 174
• Delay Time: 1.2 ns
• Supply Voltage (max): 5.25 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.25 V
• Number Of Gates: 48 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timing Characteristics
Timing characteristics for HiRel SX-A devices fall into
three categories: family-dependent, device-dependent,
and design-dependent. The input and output buffer
characteristics are common to all HiRel SX-A family
members. Internal routing delays are device-dependent.
Design dependency means actual delays are not
determined until after place-and-route of the user’s
design
determined by using the Timer utility or performing
simulation with post-layout delays.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most
timing-critical paths. Critical nets are determined by net
property assignment prior to place-and-route. Up to six
percent of the nets in a design may be designated as
critical, whereas 90 percent of the nets in a design are
typical.
Table 1-15 • Temperature and Voltage Derating Factors
1 -2 0
V
2.25
2.50
2.75
HiRel SX-A Family FPGAs
CC
is
complete.
Normalized to Worst-Case Military, T
–55°C
0.73
0.68
0.63
Delay
values
–40°C
0.74
0.69
0.64
may
then
J
= 125°C, V
0.80
0.75
0.70
0°C
Junction Temperature (T
be
v2.0
CCA
Long Tracks
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows,
columns, or modules. Long tracks employ three to five
antifuse connections. This increases capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically, up to six percent of
nets in a fully utilized device require long tracks. Long
tracks contribute approximately 4 to 8.4 ns of delay. This
additional delay is represented statistically in higher-
fanout (FO = 24) routing delays. See
page 1-21
Timing Derating
HiRel SX-A devices are manufactured with a CMOS
process. Therefore, device performance varies according
to temperature, voltage, and process changes. Minimum
timing parameters reflect maximum operating voltage,
minimum operating temperature, and best-case process
characteristics. Maximum timing parameters reflect
minimum
temperature, and worst-case processing.
= 2.25 V
25°C
0.82
0.76
0.71
to
operating
Table 1-25 on page
J
70°C
0.90
0.84
0.78
)
voltage,
1-30.
85°C
0.93
0.87
0.81
maximum
Table 1-16 on
125°C
operating
1.00
0.94
0.87