A54SX32A-PQ208 Actel, A54SX32A-PQ208 Datasheet - Page 36

• Manufacturer Part Number: A54SX32A-PQ208
• Description: FPGA - Field Programmable Gate Array 32K System Gates
• Manufacturer: Actel

Specifications of A54SX32A-PQ208

• Processor Series: A54SX32
• Core: IP Core
• Number Of Macrocells: 1800
• Maximum Operating Frequency: 238 MHz
• Number Of Programmable I/os: 174
• Delay Time: 1.2 ns
• Supply Voltage (max): 5.25 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.25 V
• Number Of Gates: 48 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TDI, I/O
Serial input for boundary scan testing and diagnostic
probe. In Flexible mode, TDI is active when the TMS pin is
set LOW
I/O when the boundary scan state machine reaches the
"logic reset" state.
TDO, I/O
Serial output for boundary scan testing. In Flexible
mode, TDO is active when the TMS pin is set LOW (refer
to
when the boundary scan state machine reaches the
"logic reset" state. When Silicon Explorer is being used,
TDO acts as an output when the checksum command is
run. It will return to a user I/O when the checksum is
complete.
TMS
The TMS pin controls the use of the IEEE 1149.1
Boundary Scan pins (TCK, TDI, TDO, and TRST). In Flexible
mode, when the TMS pin is set LOW, the TCK, TDI, and
TDO pins are boundary scan pins (refer to
page
they remain in that mode until the internal boundary
scan state machine reaches the "logic reset" state. At this
point, the boundary scan pins are released and will
function as regular I/O pins. The "logic reset" state is
reached five TCK cycles after the TMS pin is set HIGH. In
dedicated test mode, TMS functions as specified in the
IEEE 1149.1 specification.
1 -3 2
HiRel SX-A Family FPGAs
Table 1-5 on page
1
1-7). Once the boundary scan pins are in test mode,
1
1
(Table 1-5 on page
Test Data Input
Test Data Output
Test Mode Select
1-7). This pin functions as an I/O
1-7). This pin functions as an
Table 1-5 on
v2.0
TRST, I/O
Once it is configured as the JTAG Reset pin, the TRST pin
functions as an active low input that may be used to
asynchronously initialize or reset the boundary scan
circuitry. The TRST pin is equipped with an internal pull-
up resistor. This pin functions as an I/O when the
Reserve JTAG Test Reset Pin check box is cleared in the
Actel Designer software.
V
Supply voltage for I/Os. See
V
V
Supply voltage for array. See
V
CCI
CCA
CCI
CCA
power pins in the device should be connected.
power pins in the device should be connected.
Boundary Scan Reset Pin
Supply Voltage
Supply Voltage
Table 1-7 on page
Table 1-7 on page
1-10. All
1-10. All