A54SX32A-PQ208 Actel, A54SX32A-PQ208 Datasheet - Page 9

• Manufacturer Part Number: A54SX32A-PQ208
• Description: FPGA - Field Programmable Gate Array 32K System Gates
• Manufacturer: Actel

Specifications of A54SX32A-PQ208

• Processor Series: A54SX32
• Core: IP Core
• Number Of Macrocells: 1800
• Maximum Operating Frequency: 238 MHz
• Number Of Programmable I/os: 174
• Delay Time: 1.2 ns
• Supply Voltage (max): 5.25 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.25 V
• Number Of Gates: 48 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Clock Resources
The Actel high-drive routing structure provides up to
three clock networks
HCLK, is hardwired from the HCLK buffer to the clock
select MUX in each R-cell. HCLK cannot be connected to
combinatorial logic. This results in a fast propagation
path for the clock signal, enabling the 5.3 ns clock-to-out
(pad-to-pad) performance of the HiRel SX-A devices. The
hardwired clock is tuned to provide clock skew of less
than 0.3 ns worst case. If not used, this pin must be set as
LOW or HIGH on the board. It must not be left floating.
Figure 1-7
Table 1-1 •
Figure 1-7 •
The two routed clocks (CLKA and CLKB) are global clocks
that can be sourced from external pins or from internal
logic signals within the HiRel SX-A device. CLKA and
CLKB may be connected to sequential cells or to
combinatorial logic. If the CLKA or CLKB pins are not
used or sourced from signals, then these pins must be set
as LOW or HIGH on the board. They must not be left
floating, except in HiRel A54SX72A, where they can be
configured as regular I/Os.
and CLKB circuit used in HiRel A54SX32A.
Note: This does not include the clock pad for HiRel A54SX72A.
Figure 1-8 •
Hardwired Clocks (HCLK)
Routed Clocks (CLKA, CLKB)
Quadrant Clocks (QCLKA,
QCLKB, QCLKC, QCLKD)
shows the clock circuit used for the HCLK.
HiRel SX-A Clock Resources
HiRel SX-A Hardwired Load Clock Pad
HiRel SX-A Routed Clock Pads
HCLKBUF
CLKBUF
CLKBUFI
CLKINT
CLKINTI
(Table
Figure 1-8
1-1). The first clock, called
Constant Load
Clock Network
A54SX32A
HiRel
Clock Network
From Internal Logic
1
2
0
shows the CLKA
A54SX72A
HiRel
1
2
4
v2.0
In addition, the HiRel A54SX72A device provides four
quadrant clocks (QCLKA, QCLKB, QCLKC, and QCLKD),
which can be sourced from external pins or from internal
logic signals within the device. Each of these clocks can
individually drive up to a quarter of the chip, or they can
be grouped together to drive multiple quadrants. If
QCLKs are not used as quadrant clocks, they will behave
as regular I/Os. The CLKA, CLKB, and QCLK circuits for
HiRel A54SX72A are shown in
information, refer to the
page
For more information on how to use quadrant clocks in
HiRel A54SX72A, refer to the Actel
Networks in Actel Antifuse Devices
Figure 1-9 •
Other Architectural Features
Technology
The Actel HiRel SX-A family is implemented in a high-
voltage twin-well CMOS using 0.25 µm design rules. The
metal-to-metal antifuse is made up of a combination of
amorphous silicon and dielectric material with barrier
metals. It also has a programmed ("on" state) resistance
of 25 Ω with a capacitance of 1.0 fF for low signal
impedance.
Performance
The combination of architectural features described
above allows HiRel SX-A devices to operate with internal
clock frequencies of 240 MHz, enabling very fast
execution of complex logic functions. Thus, the HiRel SX-A
family is an optimal platform upon which to integrate
the functionality previously contained in multiple CPLDs.
1-31.
HiRel A54SX72A CLKA/CLKB/QCLK Pads
CLKBUF
CLKBUFI
CLKINT
CLKINTI
CLKBIBUF
CLKBIBUFI
"Pin Description" section on
QCLKBUF
QCLKBUFI
QCLKINT
QCLKINTI
QCLKBIBUF
QCLKBIBUFI
HiRel SX-A Family FPGAs
Figure
application note.
Clock Network
From Internal Logic
To Internal Logic
From Internal Logic
OE
1-9. For more
Global Clock
1-5