A54SX32A-PQ208 Actel, A54SX32A-PQ208 Datasheet - Page 6

• Manufacturer Part Number: A54SX32A-PQ208
• Description: FPGA - Field Programmable Gate Array 32K System Gates
• Manufacturer: Actel

Specifications of A54SX32A-PQ208

• Processor Series: A54SX32
• Core: IP Core
• Number Of Macrocells: 1800
• Maximum Operating Frequency: 238 MHz
• Number Of Programmable I/os: 174
• Delay Time: 1.2 ns
• Supply Voltage (max): 5.25 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.25 V
• Number Of Gates: 48 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Interconnection between these logic modules is achieved
using Actel patented metal-to-metal programmable
antifuse interconnect elements, which are embedded in
the top two layers. The antifuses are normally open
circuit and, when programmed, form a permanent low-
impedance connection.
The extremely small size of these interconnect elements
gives the HiRel SX-A family abundant routing resources
and provides excellent protection against design theft.
Reverse engineering is virtually impossible because it is
extremely difficult to distinguish between programmed
and unprogrammed antifuses. Additionally, since HiRel
SX-A is a nonvolatile single-chip solution, there is no
configuration bitstream to intercept.
The HiRel SX-A interconnect elements (the antifuses and
metal tracks) also have lower capacitance and lower
resistance than those of any other device of similar
capacity, resulting in the fastest signal propagation in
the industry for the radiation tolerance offered.
Logic Module Design
The HiRel SX-A family architecture is described as a "sea-
of-modules" architecture because the entire floor of the
device is covered with a grid of logic modules with
virtually no chip area lost to interconnect elements or
routing. Actel HiRel SX-A devices provide two types of
logic modules: the register cell (R-cell) and the
combinatorial cell (C-cell).
The R-cell
asynchronous clear, asynchronous preset, and clock
enable (using the S0 and S1 lines) control signals. The
R-cell registers feature programmable clock polarity
selectable on a register-by-register basis.
Figure 1-2 •
1 -2
Internal Logic
HiRel SX-A Family FPGAs
Connect
Direct
CLKA,
Input
CLKB,
HCLK
(Figure
R-Cell
CKS
S0
1-2) contains a flip-flop featuring
Data Input
Routed
CKP
S1
D
PSETB
CLRB
Q
Y
v2.0
This provides additional flexibility while allowing the
mapping of synthesized functions into the HiRel SX-A
FPGA. The clock source for the R-cell can be chosen from
the hardwired clock, the routed clocks, or internal logic.
The C-cell implements a range of combinatorial functions
up to five inputs
and its associated inverter function increases the number
of combinatorial functions that can be implemented in a
single module from 800 options (as in previous
architectures) to more than 4,000 in the HiRel SX-A
architecture. An example of the improved flexibility
enabled by the inversion capability is the ability to
implement a three-input exclusive-OR function into a
single C-cell. This facilitates construction of 9-bit parity-
tree functions with 1.9 ns of propagation delay. At the
same time, the C-cell structure is extremely synthesis
friendly, simplifying the overall design and reducing
synthesis time.
Figure 1-3 •
Chip Architecture
The HiRel SX-A family chip architecture provides a
unique approach to module organization and chip
routing that delivers the best register/logic mix for a
wide variety of new and emerging applications.
Module Organization
Actel has arranged all C-cell and R-cell logic modules into
horizontal banks called clusters. There are two type of
clusters: Type 1 clusters contain two C-cells and one
R-cell, and Type 2 clusters contain one C-cell and two
R-cells.
To increase design efficiency and device performance,
Actel has further organized these modules into
SuperClusters
SuperCluster is a two-wide grouping of Type 1 clusters. A
D0
D1
D2
D3
DB
C-Cell
(Figure 1-4 on page
(Figure
A0
1-3). Inclusion of the DB input
B0
Sa
1-3). A Type 1
A1
B1
Sb
Y